ADV601JS Analog Devices, ADV601JS Datasheet - Page 26

• Manufacturer Part Number: ADV601JS
• Description: Low Cost Multiformat Video Codec
• Manufacturer: Analog Devices

ADV601
DRAM Manager
The DRAM Manager provides a sorting and reordering func-
tion on the sub-band coded data between the Wavelet Kernel
and the Programmable Quantizer. The DRAM manager pro-
vides a pipeline delay stage to the ADV601. This pipeline lets
the ADV601 extract current field image statistics (min/max
pixel values, sum of pixel values, and sum of squares) used in
the calculation of Bin Widths and re-order wavelet transform
data. The use of current field statistics in the Bin Width calcula-
tion results in precise control over the compressed bit rate. The
DRAM manager manages the entire operation and refresh of the
DRAM.
The interface between the ADV601 DRAM manager and
DRAM is designed to be transparent to the user. The ADV601
DRAM pins should be connected to the DRAM as called out in
the Pin Function Descriptions section. The ADV601 requires
one 256K word by 16-bit, 60 ns DRAM. The following is a
selected list of manufacturers and part numbers. All parts can
be used with the ADV601 at all VCLK rates except where
noted. Any DRAM used with the ADV601 must meet the mini-
mum specifications outlined for the Hyper Mode DRAMs listed
in Table XIII. For DRAM Interface pins descriptions, see the
Pin Function Descriptions.
SEQUENCE FOR MALLAT BLOCK 9
FIELD 1 SEQUENCE
START OF FIELD 1 OR 2 CODE
FRAME (N)
SUB-BAND TYPE CODE
START OF BLOCK CODE
Figure 12. Hierarchical Structure of Wavelet Compressed Frame Data (Data Block Order)
FIELD 2 SEQUENCE
FRAME (N + 1)
COMPLETE BLOCK (INDIVIDUAL) SEQUENCE STRUCTURE
FIELD SEQUENCE STRUCTURE
SEQUENCE FOR MALLAT BLOCK 20
BIN WIDTH QUANTIZER CODE
BIN WIDTH QUANTIZER CODE
VERTICAL INTERFACE TIME CODE
FRAME (N + 2)
FIRST BLOCK SEQUENCE STRUCTURE
–26–
TIME
Manufacturer Part Number
Toshiba
NEC
NEC
Hitachi
Compressed Data-Stream Definition
Through its Host Interface the ADV601 outputs (during en-
code) and receives (during decode) compressed digital video
data. This stream of data passing between the ADV601 and the
host is hierarchically structured and broken up into blocks of
data as shown in Figure 12. Table IV shows pseudo code for a
video data transfer that matches the transfer order shown in
Figure 12 and uses the code names shown in Table XVI. The
blocks of data listed in Figure 12 correspond to wavelet com-
pressed sections of each field illustrated in Figure 13 as a modified
Mallat diagram.
DATA FOR MALLAT BLOCK 6
DATA FOR MALLAT BLOCK
(CONTINUOUS STREAM OF FRAMES)
(STREAM OF MALLAT
BLOCK SEQUENCES)
Table XIII. ADV601 Compatible DRAMs
FIRST BLOCK SEQUENCE
COMPLETE BLOCK SEQUENCE ORDER
HM514265CJ-60
TC514265DJ/DZ/DFT-60
PD424210ALE-60
PD42S4210ALE-60
SEQUENCE FOR MALLAT BLOCK 3
COMPLETE BLOCK SEQUENCE
FRAME (N + M)
Notes
None
None
CBR Self Refresh
feature of this prod-
uct is not needed by
the ADV601.
None
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