adv601 Analog Devices, Inc., adv601 Datasheet

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... A review of the General Theory of Operation and Applying the ADV601 sections will help you get the most use out of the ADV601 in any given application. The ADV601 accepts component digital video through the Video Interface and outputs a compressed bit stream though the Host Interface in Encode Mode ...

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... PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 16 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Compressed Data-Stream Definition . . . . . . . . . . . . . . . . 26 APPLYING THE ADV601 . . . . . . . . . . . . . . . . . . . . . . . . . 32 Using the ADV601 in Computer Applications . . . . . . . . 32 Using the ADV601 in Stand-Alone Applications . . . . . . . 32 Connecting the ADV601 to Popular Video Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GETTING THE MOST OUT OF ADV601 . . . . . . . . . . . 35 ADV601 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 36 TEST CONDITIONS ...

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... These options are outlined on in the Applying the ADV601 section. The DSP serial port interface (SPORT) enables performance of Bin Width calculations on a DSP instead of the host. The ADV601 transfers current video field statistics to the DSP and receives Bin Width data from the DSP as packet I/O through the DSP Inter- face ...

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... High quality filtered/decimated images can be extracted/created without computational overhead. Through leverage of these key points, the ADV601 not only compresses video, but offers a host of application features. Please see the Applying the ADV601 section for details on getting the most out of the ADV601’s sub-band coding architecture in different applications BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128 ...

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... Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) REV. 0 Figure 5. Modified Mallat Diagram of Image –5– ADV601 ...

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... ADV601 LUMINANCE AND COLOR COMPONENTS (EACH SEPARATELY) HIGH LOW PASS IN PASS HIGH LOW PASS IN PASS IN BLOCK HIGH LOW HIGH PASS IN PASS IN PASS BLOCK BLOCK BLOCK HIGH PASS BLOCK ...

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... Mallat block data and (2) levels of quantization range widely from high to low frequency block. (Note that the fill is based on a log formula.) The relation between actual ADV601 bin width factors and the Mallat block fill pattern in Figure 8 appears in Table II. 39 ...

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... Widths during decode because the Bin Width is stored in the 0x011a compressed image during encode. 0x011a 0x0066 PROGRAMMER’S MODEL 0x0066 A host device configures the ADV601 using the Host I/O Port. 0x0055 The host reads from status registers and writes to control regis- 0x0054 ters through the Host I/O Port. 0x0054 0x0054 ...

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... RESERVED 0xC INDIRECT (INTERNALLY INDEXED) REGISTERS {ACCESS THESE REGISTERS THROUGH THE INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} Figure 9. Map of ADV601 Direct and Indirect Registers REV. 0 DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS BYTE 2 BYTE 1 INDIRECT REGISTER ADDRESS INDIRECT REGISTER DATA COMPRESSED DATA ...

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... Interrupt Mask / Status Register Direct (Read/Write) Register Byte Offset 0x0C This 16-bit register contains interrupt mask and status bits that control the state of the ADV601’s HIRQ pin. With the seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions that are ORed together to determine the output of the HIRQ pin ...

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... Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can be caused by a defective DRAM, the inability of the Host to keep up with the ADV601 compressed data stream, or bit errors in the data stream. Note that the ADV601 recovers from this condition without host intervention. ...

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... Normal operation 1 Software Reset. This bit is set on hardware reset and must be cleared before the ADV601 can begin processing. (reset value) When this bit is set during encode, the ADV601 completes processing the current field then suspends operation until the SWR bit is cleared. When this bit is set during decode, the ADV601 suspends operation immediately and does not resume operation until the SWR bit is cleared ...

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... Indirect (Write Only) Register Index 0x05 This register holds the setting for the vertical end of the ADV601’s active video area. If the value is larger than the max size of the selected video mode, the ADV601 uses the max size of the selected mode for VEND. ...

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... These registers let the Host or DSP read sum of squares statistics from the ADV601; using these values (with the Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV601 indicates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin ...

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... Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined at reset). [15:0] Bin Width Values, BW[15:0] [15:0] Reciprocal Bin Width Values, RBW[15:0] REV. 0 –15– ADV601 ...

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... Mode). The pin operates as follows: • Output (Master) HI during Field1 lines of video and LO otherwise • Input (Slave this input indicates Field1 lines of video Encode or Decode. This output pin indicates the coding mode of the ADV601 and operates as follows: • LO Decode Mode (Video Interface is output) • ...

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... TXData pin DSP is present, tie this pin to ground. This pin is compatible with 30 pF loads. The RXD pin is for serial data input to the ADV601. Serial data consists of 16- bit words that are transferred most-significant-bit first. Note that the Mode Control register must be set to indicate whether or not the external DSP is present. Serial Data Clock (VCLK/4). Connect this pin to an optional, external DSP’ ...

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... The DIRQ pin on the ADV601 provides an optional method for signalling the DSP that a new packet of field statistics is being transmitted and can be used system- wide for signalling that a new video field has begun. Because the ADV601 asserts DIRQ throughout statistics transmission and bin width reception, the DSP’s inter- rupts should be set for edge-sensitivity ...

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... Data register); so the FIFO location only advances when and if the • host reads or writes the MSB of a FIFO location. • The ADV601 advances to the next 16-bit indirect register after the BE1 pin • is asserted then de-asserted; so the register selection only advances when • ...

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... Mode Control register. ADV601 Chip Reset. Asserting this pin returns all registers to reset state. Note that the ADV601 must be reset at least once after power-up with this active low signal input. For more information on reset, see the SWR bit description. ...

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... In CCIR-656 mode, this control is set to Uni- polar, since the color components are offset by 128. Note that it is likely the ADV601 will function if this control is in the wrong state, but compression performance will be degraded important to set this bit correctly. ...

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... Clocks and Strobes All video data, whether “lanes” of video are used, are synchronous to the video clock (VCLK). The rising edge of VCLK is used to clock all data into the ADV601. Synchronization and Blanking Pins Three signals, which can be configured as inputs or outputs, are used for video frame and field horizontal synchronization and blanking ...

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... The ADV601 completely manages the generation and timing of these pins. signals are VSYNC, HSYNC, CREF and FIELD. In general, when the ADV601 is configured as an encoder, these signals will all be inputs. When the ADV601 is configured as a decoder, these signals will be outputs. There are special cases for this described in Table X ...

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... ADV601 Video Formats — Multiplexed Philips Video The ADV601 supports a hybrid mode of operation that is a cross between standard dual lane Philips and single lane CCIR-656. In this mode, video data is multiplexed in the same fashion in CCIR-656, but the values 0 and 255 are not reserved as signaling values. In- stead, external HSYNC and VSYNC pins are used for signaling and video synchronization ...

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... The DSP transfers the bin width and reciprocal bin width packet of eighty-four 16-bit words on the ADV601’s RXD pin using a pulse on the ADV601’ indicate the begin- ning, most-significant-bit first, of each word. The bin width and reciprocal bin width transfer for the first field occurs before the end of the next field ...

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... All parts can be used with the ADV601 at all VCLK rates except where noted. Any DRAM used with the ADV601 must meet the mini- mum specifications outlined for the Hyper Mode DRAMs listed in Table XIII. For DRAM Interface pins descriptions, see the Pin Function Descriptions ...

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... Block Sequence: #SOB1, #SOB2, #SOB3, #SOB4 or #SOB5 <BW> <Huff_Data> REV. 0 “Frame N; Field 1” “Frame N; Field 2” “Frame N+1; Field 1” “Frame N+1; Field 2” “Frame N+M; Field 1” “Frame N+M; Field 2” “Required in decode to let the ADV601 know the sequence of fields is complete.” –27– ADV601 ...

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... A pseudo code bit stream example for one complete field of video is shown in Table XV. A pseudo code bit stream example for one sequence of fields is shown in Table XVI. An example listing of a field of video in ADV601 bitstream format appears in Table XVIII. Y COMPONENT 6 3 ...

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... Mallat block 30 data— Typical BW = 0x00E4 Mallat block 21 data—Typical BW = 0x0301 Mallat block 27 data—Typical BW = 0x0281 Mallat block 24 data—Typical BW = 0x0281 Mallat block 3 data—Typical BW = 0x23D5 For Mallat Block Number /* Mallat block 6 data */ /* Mallat block 6 data */ /* Required in decode to end field sequence*/ –29– ADV601 ...

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... ADV601 Table XVII. ADV601 Field and Block Delimiters (Codes) Code Name Code #SOF1 0xffffffff40000000 #SOF2 0xffffffff41000000 <VITC> (96 bits) <TYPE1> 0x81 <TYPE2> 0x82 <TYPE3> 0x83 <TYPE4> 0x84 #SOB1 0xffffffff81 #SOB2 0xffffffff82 #SOB3 0xffffffff83 #SOB4 0xffffffff84 #SOB5 0xffffffff8f Description (Align all #Delimiter Codes to 32-Bit Boundaries) Start of Field delimiter identifies Field1 data ...

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... NOTE 1 This table shows ADV601 compressed data for one field in a color ramp video sequence. The SOF# and SOB# codes in the data are in bold text. Bit Error Tolerance Bit error tolerance is ensured because a bit error within a Huffman coded stream does not cause #delimiter symbols to be misread by the ADV601 in decode mode ...

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... According to the Brooktree data sheet, the Mode B Asynchro- nous Pixel Interface (API) must be used to give a continuous stream of active and blanked data as required by the ADV601. An external circuit is used to generate RDEN (read enable) pin input for the Bt819A, and the ADV601 VCLKO signal must be divided by two ...

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... BE1 BE2 TOSHIBA TC514265DJ/DZ/DFT-60 BE3 NEC uPD424210ALE-60 ADV601 NEC uPD42S4210ALE-60 HITACHI HM514265CJ-60 VCLKO* CS ANY DRAM USED WITH THE ADV601 MUST MEET THE MINIMUM SPECIFICATIONS RD OUTLINED FOR THE HYPER MODE DRAMS LISTED WR FIFO_ERR STATS_R 29.50000MHz PAL OR HIRQ 24.54543MHz NTSC LCODE VCLK ...

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... Because the ADV7175 has a CCIR-656 interface, it connects directly with the ADV601 without “glue” logic. Note that the ADV7175 can only be used at CCIR-601 sampling rates. The ADV7175 example circuit, which appears in Figure 20, is used in this configuration on the ADV601 Video Lab demon- stration board. VCLK VCLK VCLKO (MODE 0 & ...

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... This effect achieved by attenuation of luminance blocks. Mixing of Two or More Images Blocks from different images can be mixed into the bit stream and then sent to the ADV601 during decode. The result is high quality mixing of different images. This also provides the capa- bility to fade from one image to the next. ...

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... Permanent damage may occur to devices subjected to high energy electrostatic discharges. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. The ADV601 latchup immunity has been demonstrated at 100 mA/– all pins when tested to industry standard/JEDEC methods. Min 4 ...

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... OL Figure 23. Test Condition Voltage Reference and Device Loading TIMING PARAMETERS This section contains signal timing information for the ADV601. Timing descriptions for the following items appear in this section: • Clock signal timing • Video data transfer timing (CCIR-656, Gray Scale/Philips, and Multiplexed Philips formats) • ...

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... ADV601 (I) VCLK (O) VCLKO (VCLK2 = 0) (I) VCLKO (VCLK2 = 1) NOTE: USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS. DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE. CCIR-656 Video Format Timing The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal), and frame (vertical) data in CCIR-656 video mode ...

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... Figure 27. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLK0. REV. 0 –39– ADV601 ...

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... ADV601 Gray Scale/Philips Video Timing The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal) and frame (vertical) data in Gray Scale or Philips video modes. All output values assume a maximum pin loading of 50 pF. Note that in timing diagrams for Gray Scale/Philips video, the label CTRL indicates the VSYNC, HSYNC and FIELD pins. Table XXV. Gray Scale/Philips Video— ...

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... ASSERTED t CTRL_ESGP_S (I) CREF t CREF_ESGP_S Figure 31. Gray Scale/Philips Video—Encode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA_EMGP_H t CTRL_EMGP_D t CREF_EMGP_OH t CREF_EMGP_D VALID t VDATA_ESGP_H t CTRL_ESGP_H t CREF_ESGP_H –41– ADV601 Min Max Unit 2 N N N N/A ns VALID ASSERTED Min Max ...

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... ADV601 Figure 32. Gray Scale/Philips Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note: For CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLK0. –42– REV. 0 ...

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... CTRL Signals, Decode Slave Multiplexed Philips, Hold CTRL_DSM_H (O) VCLKO (O) VDATA (I) CTRL Figure 34. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA_DMM_D VALID t CTRL_DMM_D VALID t VDATA_DSM_OH t VDATA_DSM_D VALID t CTRL_DSM_S –43– ADV601 Min Max N N/A N N/A VALID VALID Min Max N N/A 2 N/A 42 ...

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... ADV601 Table XXXI. Multiplexed Philips Video —Encode and Master Pixel (YCrCb) Timing Parameters Parameter Description t VDATA Bus, Encode Master Multiplexed Philips, Setup VDATA_EMM_S t VDATA Bus, Encode Master Multiplexed Philips, Hold VDATA_EMM_H t CTRL Signals, Encode Master Multiplexed Philips, Delay CTRL_EMM_D t CTRL Signals, Encode Master Multiplexed Philips, Output Hold ...

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... Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601’s direct registers, except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are slower than access timing for the Compressed Data register ...

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... ADV601 Table XXXIV. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters Parameter Description WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK) t WR_D_WRC WR Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK) t WR_D_PWA WR Signal, Direct Register, Pulse Width Deasserted (at 27 MHz VCLK) ...

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... Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac- cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers ...

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... ADV601 Table XXXVI. Host (Compressed Data) Write Timing Parameters Parameter Description WR Signal, Compressed Data Direct Register, Write Cycle time t WR_CD_WRC WR Signal, Compressed Data Direct Register, Pulse Width Asserted t WR_CD_PWA WR Signal, Compressed Data Direct Register, Pulse Width Deasserted t WR_CD_PWD t ADR Bus, Compressed Data Direct Register, Write Setup ...

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... ADV601’s DSP interface. Whenever an ADV601’s serial port is inactive, the codec’s TXD pin is three-stated and the codec ignores the state of the RXD pin. Figure 41 illustrates the ADV601 serial interface’s signal, sample and frame relationships for the transmit and receive modes. ...

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... ADV601 Pin Pin Pin Name Type 1 DATA4 I/O 2 DATA3 I/O 3 DATA2 I/O 4 DATA1 I/O 5 DATA0 I/O 6 VDD POWER 7 GND GROUND ADR1 I 12 ADR0 I 13 GND GROUND BE3 14 I BE2 15 I BE1 16 I BE0 GND GROUND RESET VDD POWER ACK ...

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... TCLK GND 35 36 RXD GND VDD 39 40 DADR8 REV. 0 PIN CONFIGURATION ADV601 PQFP TOP VIEW (Pins Down) –51– ADV601 120 GND 119 VDATA0 118 VDATA1 117 VDATA2 116 VDATA3 115 VDATA4 114 VDATA5 113 VDD 112 GND 111 VDATA6 ...

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... ADV601 0.041 (1.03) 0.035 (0.88) TYP 0.029 (0.73) SEATING PLANE 0.004 (0.10) 0.010 (0.25) Part Number Ambient Temperature Range ADV601JS +70 C NOTES Commercial temperature range ( +70 C PQFP (Plastic Quad Flatpack). OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 160-Lead PQFP (S-160) 1.238 (31.45) 1.228 (31.20) TYP SQ 1 ...