AT89LS53 ATMEL Corporation, AT89LS53 Datasheet - Page 14

• Manufacturer Part Number: AT89LS53
• Description: 8-Bit Microcontroller with 12K Bytes Flash
• Manufacturer: ATMEL Corporation

Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu-
lar I/0 pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 3
MHz at a 12 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 rollovers will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
Figure 6. SPI Block Diagram
4-262
Clock-Out Frequency
SPI STATUS REGISTER
=
OSCILLATOR
÷4÷16÷64÷128
------------------------------------------------------------------------------------------ -
4
SELECT
AT89LS53
DIVIDER
SPI CONTROL
65536
Oscillator Frequency
SPI INTERRUPT
–
SPI CLOCK (MASTER)
REQUEST
RCAP2H,RCAP2L
MSTR
SPE
8
INTERNAL
MSB
DATA BUS
8/16-BIT SHIFT REGISTER
8
READ DATA BUFFER
8
SPI CONTROL REGISTER
UART
The UART in the AT89LS53 operates the same way as the
UART in the AT89C51, AT89C52 and AT89C55. For fur-
ther information, see the October 1995 Atmel Microcontrol-
ler Data Book, page 2-49, section titled, “Serial Interface.”
Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the AT89LS53 and periph-
eral devices or between several AT89LS53 devices. The
AT89LS53 SPI features include the following:
• Full-Duplex, 3-Wire Synchronous Data Transfer
• Master or Slave Operation
• 1.5-MHz Bit Frequency (max.)
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wakeup from Idle Mode (Slave Mode Only)
CLOCK
LOGIC
LSB
CLOCK
S
M
M
S
S
M
MISO
MOSI
P1.6
P1.5
SCK
P1.4
1.7
SS