AT89LS53 ATMEL Corporation, AT89LS53 Datasheet - Page 18
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AT89LS53
Manufacturer Part Number
AT89LS53
Description
8-Bit Microcontroller with 12K Bytes Flash
Manufacturer
ATMEL Corporation
Datasheet
1.AT89LS53.pdf
(31 pages)
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Program Memory Lock Bits
The AT89LS53 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
Lock Bit Protection Modes
Notes:
Programming the Flash
Atmel’s AT89LS53 Flash Microcontroller offers 12K bytes
of in-system reprogrammable Flash Code memory.
The AT89LS53 is normally shipped with the on-chip Flash
Code memory array in the erased state (i.e. contents =
FFH) and ready to be programmed. This device supports a
High-Voltage (12V) Parallel programming mode and a Low-
Voltage (2.7 to 6.0V) Serial programming mode. The serial
programming mode provides a convenient way to down-
load the AT89LS53 inside the user’s system. The parallel
programming mode is compatible with conventional third
party Flash or EPROM programmers.
The Code memory array occupies one contiguous address
space from 0000H to 2FFFH.
The Code array on the AT89LS53 is programmed byte-by-
byte in either programming mode. An auto-erase cycle is
provided with the self-timed programming operation in the
serial programming mode. There is no need to perform the
Chip Erase operation to reprogram any memory location in
the serial programming mode unless any of the lock bits
have been programmed.
In the parallel programming mode, there is no auto-erase
cycle. To reprogram any non-blank byte, the user needs to
use the Chip Erase operation first to erase the entire Code
memory array.
4-266
1
2
3
4
Program Lock Bits
2. P = Programmed
1. U = Unprogrammed
LB1
U
P
P
P
LB2
U
U
P
P
LB3
U
U
U
P
AT89LS53
Protection Type
No internal memory lock feature.
MOVC instructions executed from external program memory are disabled from fetching
code bytes from internal memory. EA is sampled and latched on reset and further
programming of the Flash memory (parallel or serial mode) is disabled.
Same as Mode 2, but parallel or serial verify are also disabled.
Same as Mode 3, but external execution is also disabled.
(1) (2)
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Once programmed, the lock bits can only be unpro-
grammed with the Chip Erase operations in either the par-
allel or serial modes.
Parallel Programming Algorithm
To program and verify the AT89LS53 in the parallel pro-
gramming mode, the following sequence is recommended:
1. Power-up sequence:
2. Set PSEN pin to “L”
3. Apply the appropriate combination of “H” or “L” logic
4. Apply the desired byte address to pins P1.0 to P1.7
5. Raise EA/V
6. Pulse ALE/PROG once to program a byte in the
Apply power between V
Set RST pin to “H”.
Apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait
for at least 10 milliseconds.
ALE pin to “H”
EA pin to “H” and all other pins to “H”.
levels to pins P2.6, P2.7, P3.6, P3.7 to select one of
the programming operations shown in the Flash
Programming Modes table.
and P2.0 to P2.5.
Apply data to pins P0.0 to P0.7 for Write Code opera-
tion.
erase or verification.
Code memory array, or the lock bits. The byte-write
cycle is self-timed and typically takes 1.5 ms.
PP
to 12V to enable Flash programming,
CC
and GND pins.