AT89S51-24SC ATMEL Corporation, AT89S51-24SC Datasheet - Page 12

• Manufacturer Part Number: AT89S51-24SC
• Description: 8-bit Microcontroller with 4K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Program
Memory Lock
Bits
Programming
the Flash –
Parallel Mode
12
AT89S51
Table 5. Status of External Pins During Idle and Power-down Modes
The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in the following table.
Table 6. Lock Bit Protection Modes
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during
reset. If the device is powered up without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of EA must agree with the current
logic level at that pin in order for the device to function properly.
The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compati-
ble with conventional third-party Flash or EPROM programmers.
The AT89S51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89S51, the address, data, and control
signals should be set up according to the Flash Programming Modes table (Table 7) and
Figures 4 and 5. To program the AT89S51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle.
During a write cycle, an attempted read of the last byte written will result in the complement of
the written data on P0.7. Once the write cycle has been completed, true data is valid on all out-
puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has
been initiated.
Mode
Idle
Idle
Power-down
Power-down
1
2
3
4
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Program Lock Bits
LB1
U
P
P
P
PP
Program Memory
Internal
External
Internal
External
to 12V.
LB2
U
U
P
P
LB3
U
U
U
P
ALE
Protection Type
No program lock features
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further
programming of the Flash memory is disabled
Same as mode 2, but verify is also disabled
Same as mode 3, but external execution is also disabled
1
1
0
0
PSEN
1
1
0
0
PORT0
Float
Float
Data
Data
PORT1
Data
Data
Data
Data
Address
PORT2
Data
Data
Data
2487B–MICRO–12/03
PORT3
Data
Data
Data
Data