ADUC702X Analog Devices, ADUC702X Datasheet - Page 60
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ADUC702X
Manufacturer Part Number
ADUC702X
Description
Precision Analog Microcontroller 12-bit Analog I/O/ ARM7TDMI MCU
Manufacturer
Analog Devices
Datasheet
1.ADUC702X.pdf
(80 pages)
- Current page: 60 of 80
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ADuC702x Series
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
General call enable bit
Set by user to address every device on the I
Cleared by user to operate in normal mode
Reserved
Master enable bit
Set by user to enable the master I
Cleared by user to disable the master I
Slave enable bit
Set by user to enable the slave I
I2C0ID1, I2C0ID2 and I2C0ID3. if the device address is recognised the part will participate in the slave transfer sequence
Cleared by user to disable the slave I
Description
Transmit FIFO flush
Set by user to flush the transmit FIFO
Cleared by user to operate in normal mode
Slave busy
Set automatically if the slave is busy
Cleared automatically
No ACK
Set if master asking for data and no data is available
Cleared automatically
Slave receive FIFO overflow
Set automatically if the slave receive FIFO is overflowing
Cleared automatically by reading I2C0SRX
Slave receive IRQ
Set after receiving data
Cleared automatically by reading the I2C0SRX register
Slave transmit IRQ
Set at the end of a transmission
Cleared automatically by writing to the I2C0STX register
Slave transmit FIFO underflow
Set automatically if the slave transmit FIFO is underflowing
Cleared automatically by writing to the I2C0STX register
Slave transmit FIFO empty
Set automatically if the slave transmit FIFO is empty
Cleared automatically by writing to the I2C0STX register
Description
Transmit FIFO flush
Set by user to flush the transmit FIFO
Cleared by user to operate in normal mode
Master busy
Set automatically if the master is busy
Cleared automatically
Arbitration loss
Set in multi-master mode if another master has the bus
Cleared when the bus becomes available
2
C channel. A slave transfer sequence will be monitored for the device address in I2C0ID0,
2
C channel
Table 50: I2C0MSTA MMR Bit Descriptions
Table 49: I2C0SSTA MMR Bit Descriptions
2
C channel
2
C channel
2
C bus
Rev. PrB | Page 60 of 80
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