SAK-C164CI-8RM Infineon Technologies AG, SAK-C164CI-8RM Datasheet - Page 64
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SAK-C164CI-8RM
Manufacturer Part Number
SAK-C164CI-8RM
Description
16-Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheets
1.SAK-C164CI-8RM.pdf
(79 pages)
2.SAK-C164SL-6RM.pdf
(79 pages)
3.SAK-C164CL-8R25M.pdf
(79 pages)
- Current page: 64 of 79
- Download datasheet (2Mb)
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
Data Sheet
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
A
43
44
45
46
47
48
49
50
51
52
54
56
+
t
CC -4 +
CC –
CC –
CC 30 +
CC 50 +
CC 26 +
CC 20 +
CC 20 +
SR –
SR –
SR 0
SR –
C
+
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
= 25 MHz
t
t
t
t
t
t
A
60
C
C
C
F
F
max.
–
0
20
16 +
36 +
–
–
–
–
20 +
–
–
t
t
t
C
C
F
1 / 2TCL = 1 to 25 MHz
min.
-4
+
–
–
–
–
2TCL - 10
+
3TCL - 10
+
2TCL - 14
+
0
–
2TCL - 20
+
2TCL - 20
+
Variable CPU Clock
t
t
t
t
t
t
A
C
C
C
F
F
max.
–
0
TCL
2TCL - 24
+
3TCL - 24
+
–
–
–
–
2TCL - 20
+
–
–
t
t
t
C
C
F
C164CL/SL
V2.0, 2001-05
C164CI/SI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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