AT49BV4096-15RC ATMEL Corporation, AT49BV4096-15RC Datasheet - Page 2

• Manufacturer Part Number: AT49BV4096-15RC
• Description: 4-Megabit 256K x 16 3-volt Only CMOS Flash Memory
• Manufacturer: ATMEL Corporation

contention. Reprogramming the AT49BV4096/LV4096 is
performed by first erasing a block of data and then pro-
gramming on a word-by-word basis.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase op-
erations. There are two 8K word parameter block sections
and one sector consisting of the boot block and the main
memory array block. The AT49BV4096/LV4096 is pro-
grammed on a word-by-word basis.
The device has the capability to protect the data in the
boot block; this feature is enabled by a command se-
Block Diagram
Device Operation
READ: The AT49BV4096/LV4096 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the ad-
dress pins is asserted on the outputs. The outputs are put
in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in prevent-
ing bus contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode de-
pending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command se-
quences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying
a low pulse on the WE or CE input with CE or WE low
(respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
2
AT49BV/LV4096
quence. Once the boot block programming lockout feature
is enabled, the data in the boot block cannot be changed
when input levels of 3.6 volts or less are used. The typical
number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
During a chip erase, sector erase, or word programming,
the V
RESET: A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
When a high level is reasserted on the RESET pin, the
device returns to the Read or Standby mode, depending
upon the state of the control inputs. By applying a 12V
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block program lock-
out feature has been enabled (see Boot Block Program-
ming Lockout Override section).
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of memory bits is a logical “1”.
The entire device can be erased by using the Chip Erase
command or individual sectors can be erased by using the
Sector Erase commands.
CHIP ERASE: The entire device can be erased at one
time by using the 6-byte chip erase software code. After
the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are re-
quired. The maximum time to erease the chip is t
PP
pin must be at 5V
10%.
EC
.