M24128 STMicroelectronics, M24128 Datasheet - Page 6

• Manufacturer Part Number: M24128
• Description: 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
• Manufacturer: STMicroelectronics

M24256, M24128
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
Table 5. Most Significant Byte
Note: 1. b15 is treated as Don’t Care on the M24256 series.
Table 6. Least Significant Byte
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for two address bytes. The memory re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
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b15
b7
b15 and b14 are Don’t Care on the M24128 series.
b14
b6
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
b13
b5
b12
b4
b11
b3
DEV SEL
DEV SEL
ACK
b10
b2
DATA IN N
R/W
R/W
b9
b1
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
b8
b0
ACK
ACK
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
ACK
ACK
DATA IN 2
AI01106B