M24128 STMicroelectronics, M24128 Datasheet - Page 7

• Manufacturer Part Number: M24128
• Description: 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
• Manufacturer: STMicroelectronics

Figure 7. Write Cycle Polling Flowchart using ACK
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become over-
written (in a way not formally specified in this data
sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
First byte of instruction
with RW = 0 already
decoded by M24xxx
ReSTART
STOP
NO
NO
DEVICE SELECT
START Condition
WRITE Cycle
Addressing the
with RW = 0
Operation is
in Progress
th
Returned
Memory
ACK
Next
bit” time
YES
WRITE Operation
Proceed
YES
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (t
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
– Step 2: if the memory is busy with the internal
followed by a Device Select Code (the first byte
of the new instruction).
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
Byte Address
Send
w
) is shown in Table 10, but the
Random Address
READ Operation
Proceed
AI01847
M24256, M24128
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