W25P243A-4A Winbond, W25P243A-4A Datasheet

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W25P243A-4A

Manufacturer Part Number
W25P243A-4A
Description
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Manufacturer
Winbond
Datasheet
GENERAL DESCRIPTION
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536
address counter supports both Pentium
executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by
the FT pin. A snooze mode can reduce power dissipation.
W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/ CE3 .
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
BLOCK DIAGRAM
Synchronous operation
High-speed access time: 4.5/5/6 nS (max.)
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
64K
64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
BW(8:1)
CE(3:1)
A(15:0)
ADSC
ADSP
BWE
ADV
LBO
CLK
GW
OE
ZZ
64 BURST PIPELINED HIGH-SPEED
REGISTER
REGISTER
CONTROL
INPUT
LOGIC
burst mode and linear burst mode. The mode to be
- 1 -
REGISTER
DATA I/O
Pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
Support 2T/1T mode
Packaged in 128-pin QFP and TQFP
64K X 64
ARRAY
CORE
CMOS STATIC RAM
Publication Release Date: August 1999
I/O(64:1)
W25P243A
Revision A3

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W25P243A-4A Summary of contents

Page 1

... LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduce power dissipation. W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the device is deselected by CE2/ CE3 . This device supports 3-1-1-1-2-1-1 two-bank, back-to-back burst read cycle. ...

Page 2

... W25P243A / / / / 102 ...

Page 3

... Snooze pin for low-power state, internal pull low Lower address burst order Connected to V Connected to V linear mode. I/O power supply I/O ground Power supply Ground Reserved pin, don't use these pins No connection - 3 - W25P243A DESCRIPTION : Device is in linear mode unconnected: Device is in non- DD Publication Release Date: August 1999 Revision A3 ...

Page 4

... FUNCTIONAL DESCRIPTION The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. ...

Page 5

... W25P243A DATA ADSC ADV Hi-Z BW6 BW5 BW4 BW3 BW2 ...

Page 6

... W25P243A BW5 BW4 BW3 BW2 BW1 ...

Page 7

... I CYC Unselected mode defined in truth table (min.) /V (max min. CYC ZZ mode, T min. CYC = 3.3V SYM. CONDITIONS I/O OUT - 7 - W25P243A UNIT V V +0.5 V DDQ 1 MIN. TYP. MAX. UNIT -0.5 - +0.8 +2 +0.3 -10 - +10 - 0.4 2 ...

Page 8

... ADVS ADV Setup Time T ADVH ADV Hold Time 1. pF 3.3V OUTPUT 30 pF Including Jig and Scope (For T T KHZ, KLZ, 3.0V 90% 90% 10% 10 all timings measured in pipelined mode) A W25P243A-4A W25P243A-5 MIN. MAX. MIN. MAX. 2.0 - 2.0 - 1.0 - 1.0 - 2.0 - 2.0 - 1.0 - 1.0 - 2.0 - 2.0 - 1 W25P243A ...

Page 9

... In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode. 4. Configuration signals LBO and FT are static and should not be changed during operation. SYM. W25P243A-4A W25P243A-5 MIN. ...

Page 10

... High-Z Data-In DON'T CARE UNDEFINED Burst Read T CYC ADSP is blocked by CE1 inactive T ADCH ADCS Suspend Burst RD2 CE1 masks ADSP T OHZ W25P243A Pipelined Read Unselected ADSC initiated read RD3 Unselected with CE2 KHZ ...

Page 11

... WR2 CE1 masks ADSP CE2 / CE3 only sampled with ADSP or ADSC T DH BW[4:1] are applied only to first cycle of WR2 W25P243A Write Unselected ADSC initiated write WR3 WR3 Unselected with CE2 2d 3a Publication Release Date: August 1999 Revision A3 ...

Page 12

... ADSP is blocked by CE1 inactive T ADSC initiated read ADCH Suspend Burst WR1 RD2 WR1 CE2 / CE3 only sampled with ADSP or ADSC T OHZ W25P243A Unselected CE1 masks ADSP Unselected with CE3 KHZ ...

Page 13

... CE3 OE T Data-Out High-Z T KLZ Data-In High-Z ZZ DON'T CARE UNDEFINED Snooze -with Data Retention T CYC ADVH OHZ OLZ KHZ KQ T ZZS - 13 - W25P243A Read RD2 RD T ZZR Publication Release Date: August 1999 Revision A3 ...

Page 14

... Dual Bank Burst Read Cycle CLK Select Bank 0 ADSP ADSC ADV Read 1 A[31:3] GW BWE BW[8:1] CE1 CE[3:2] Active Bank 0 CE[3:2] Non- Active Bank 1 OE D[63:0] Bank 0 D[63:0] Bank 1 DON'T CARE UNDEFINED Select Bank 1 Non- Active Activ W25P243A Select Bank 0 Read 2 Read 3 Active Non- Active ...

Page 15

... W25P243AF-6 6 W25P243AD-4A 4.5 W25P243AD-5 5 W25P243AD-6 6 Notes 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. OPERATING STANDBY ...

Page 16

... A 0.004 0. 0.101 0.107 0.113 2.57 2. 0.006 0.008 0.010 0.15 0.20 c 0.006 0.10 0.15 0.004 0.010 D 13.90 14.00 0.547 0.551 0.555 E 19.90 20.00 20.10 0.783 0.787 0.791 e 0.020 0.50 0.669 0.685 H 0.677 17.00 17.20 D 0.905 0.921 H 0.913 23.00 23.20 E 0.039 0.023 0.031 0.60 0.80 L 0.071 L 0.063 1.40 1.60 0.055 1 y 0.004 W25P243A Detail F 1 Max. 3.40 2.87 0.25 0.25 14.10 17.40 23.40 1.00 1.80 0.10 12 ...

Page 17

... D 14.00 0.547 0.551 0.555 13.90 E 19.90 20.00 20.10 0.783 0.787 0.791 e 0.020 0.50 H 0.626 0.634 0.630 15.90 16. 0.862 0.870 22.00 22.10 0.866 21.90 E 0.030 L 0.024 0.45 0.60 0.018 L 0.039 1. 0.004 W25P243A Detail F 1 Max. 1.60 1.45 0.27 0.25 14.10 16.10 0.75 0.10 12 Publication Release Date: August 1999 Revision A3 ...

Page 18

... Winbond Memory Lab. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Winbond Microelectronics Corp. Kowloon, Hong Kong Winbond Systems Lab. TEL: 852-27513100 2727 N. First Street, San Jose, FAX: 852-27552064 CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 - 18 - W25P243A DESCRIPTION and CE3 functionality CE2 ...

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