W25P243A-4A Winbond, W25P243A-4A Datasheet - Page 3

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W25P243A-4A

Manufacturer Part Number
W25P243A-4A
Description
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Manufacturer
Winbond
Datasheet
PIN DESCRIPTION
CE1, CE2, CE3
BW1 BW8
I/O1 I/O64
SYMBOL
A0 A15
ADSC
ADSP
BWE
V
V
ADV
LBO
RSV
CLK
GW
V
V
NC
OE
ZZ
DDQ
SSQ
DD
SS
Input, Synchronous
I/O, Synchronous
Input, Clock
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Static
TYPE
Host address
Data Inputs/Outputs
Processor host bus clock
Chip enables
Global write
Byte write enable from cache controller
Host bus byte enables used with BWE
Output enable input
Internal burst address counter advance
Address status from Chip Set
Address status from CPU
Snooze pin for low-power state, internal pull low
Lower address burst order
Connected to V
Connected to V
linear mode.
I/O power supply
I/O ground
Power supply
Ground
Reserved pin, don't use these pins
No connection
- 3 -
SS
DD
: Device is in linear mode.
Publication Release Date: August 1999
or unconnected: Device is in non-
DESCRIPTION
W25P243A
Revision A3

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