XC18Vxxx Xilinx, XC18Vxxx Datasheet
XC18Vxxx
Related parts for XC18Vxxx
XC18Vxxx Summary of contents
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... All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea- ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation ...
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... Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Slave-Parallel/SelectMap mode. D1-D7 remain in HIGHZ state when the PROM operates in serial mode. D1-D7 can be left unconnected when the PROM is used in serial mode ...
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... Positive 3.3V supply voltage for internal logic. Positive 3.3V or 2.5V supply voltage (2) connected to the input buffers and output voltage drivers. No connects. . CCINT pins are no connects: pin 38 in 44-pin VQFP package, pin 44 in 44-pin PLCC CCINT www.xilinx.com 1-800-255-7778 20-pin 44-pin 44-pin SOIC & VQFP PLCC PLCC ( ...
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... NC 29 *See pin descriptions. DS026_12_060403 TDO GND CCO *See pin descriptions. DS026_13_060403 www.xilinx.com 1-800-255-7778 20 1 VCCINT VCCO 18 3 CLK VCCINT TDI TDO 16 5 SO20 TMS D1 Top 15 6 TCK D3 14 View ...
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... R Xilinx FPGAs and Compatible PROMs Table 2 provides a list of Xilinx FPGAs and compatible PROMs. Table 2: Xilinx FPGAs and Compatible PROMs Configuration Device Bits XC2VP2 1,305,440 XC2VP4 3,006,560 XC2VP7 4,485,472 XC2VP20 8,214,624 XC2VP30 11,364,608 XC2VP40 15,563,264 XC2VP50 19,021,472 XC2VP70 25,604,096 XC2VP100 33,645,312 XC2VP125 ...
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... Low. 2,097,152 External Programming 1,048,576 Xilinx reprogrammable PROMs can also be programmed by 524,288 the Xilinx HW-130, Xilinx MultiPRO third-party device programmer. This provides the added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes. (a) Design Security ...
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... XC18V00 family the ISP PROM product ID (36h for the XC18V04 the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic “1” as defined by IEEE Std. 1149.1. www.xilinx.com 1-800-255-7778 3 ...
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... These TAP timing characteristics are identical for both boundary-scan and ISP operations. CKMIN1 MSS MSH T T DIS DIH Figure 4: Test Access Port Timing Figure Parameter www.xilinx.com 1-800-255-7778 shows the timing relationships of the TAP signals. T DOV DS026_04_032702 4. Min Max 100 - ...
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... CCLK. If the user-programmable, dual-function D ration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this auto- matically with an on-chip pull-up resistor. Cascading Configuration PROMs For multiple FPGAs configured as a serial daisy-chain ...
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... SelectMAP CCLK CCLK DONE DONE INIT INIT PROGRAM PROGRAM TDI TDI TMS TMS TCK TDO TCK DS026 (v4.0) June 11, 2003 Product Specification R MODE PINS (See Note 1) Xilinx FPGA Slave Serial TDO DS026_08_061003 MODE PINS Xilinx Virtex-II FPGA Slave Serial/ SelectMAP TDO DS026_09_051003 ...
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... CEO D[0: OE/RESET (1) I/O (4) (1) External VCCINT VCCO I/O (3) Osc 1K 1K (4) Vcco VCCINT VCCO (4) Vcco 3.3K XC18Vxx (2) CLK 8 D[0: OE/RESET www.xilinx.com 1-800-255-7778 (2) VCCINT VCCO VCCINT VCCO DATA Cascaded CLK PROM CE OE/RESET CF (4) VCCINT VCCO VCCINT VCCO (4) Vcco XC18Vxx 4.7K CLK CEO D[0: OE/RESET (4) VCCINT 4.7K DS026_05_060403 11 ...
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... The XC18V00 PROMs have various control bits accessible by the customer. These can be set after the array has been ds026_10_061103 programmed using “Skip User Array” in Xilinx iMPACT soft- ware. The iMPACT software can set these bits to enable the optional JTAG read security, parallel configuration mode, or CF--> ...
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... Electrostatic discharge (ESD) ESD DS026 (v4.0) June 11, 2003 Product Specification XC18V00 Series In-System Programmable Configuration PROMs (1,2) Description Parameter (1) power supply to monotonically rise from 0V to nominal voltage within the specified CCINT Description www.xilinx.com 1-800-255-7778 Value Units –0.5 to +4.0 –0.5 to +5.5 –0.5 to +5.5 –65 to +150 +220 +125 Min Max Units 3 ...
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... OL = 500 µ MHz V MAX CCINT = V = GND Max CCINT V = GND CCINT V = Max CCINT V = GND CCINT V = GND 1.0 MHz V = GND OUT f = 1.0 MHz www.xilinx.com 1-800-255-7778 R Min Max Units 2 CCO - 0 0 µA - 100 µA –10 10 µA – ...
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... Low < 2 µ µ HCE OE DS026 (v4.0) June 11, 2003 Product Specification XC18V00 Series In-System Programmable Configuration PROMs T SCE CAC Description (2) (3) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 T HCE T HOE T CYC DS026_06_012000 Min Max Units - ...
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... All AC parameters are measured with V High < 2 µ µ HCE CE High < 2 µ µ HOE SCE CAC Description (2) (3) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 T HCE T HOE T CYC DS026_06_012000 Min Max Units - ...
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... Float delays are measured with loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V DS026 (v4.0) June 11, 2003 Product Specification XC18V00 Series In-System Programmable Configuration PROMs T CDF Last Bit T OCK Description (2,3) (3) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 T OCE First Bit T OOE DS026_07_020300 Min Max Units - ...
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... Float delays are measured with loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with CDF Last Bit T OCK Description (2,3) (3) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 T OCE First Bit T OOE DS026_07_020300 Min Max Units - ...
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... XC18V00 Series In-System Programmable Configuration PROMs XC18V04 VQ44 C Operating Range/Processing (1) (2) (2) XC18V01VQ44C XC18V512VQ44C XC18V01PC20C XC18V512PC20C XC18V01SO20C XC18V512SO20C XC18V04 VQ44 Operating Range/Processing (1) 18V01 S C Operating Range/Processing www.xilinx.com 1-800-255-7778 = –40°C to +85° –40°C to +85° –40°C to +85° ...
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... Updated for Spartan-IIE FPGA family. 12/06/01 3.1 Changed 02/27/02 3.2 Updated 03/15/02 3.3 Updated Xilinx software and modified 03/27/02 3.4 Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new 06/14/02 3.5 Made additions and changes to 07/24/02 3.6 Changed last bullet under 09/06/02 3.7 Multiple minor changes throughout, plus the addition of the deletion of Figure 9 ...
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... XC18V00 Series In-System Programmable Configuration PROMs Table 2. External Programming, and IDCODES to Table 5, discontinued XC18V256 density, eliminated and page 16. Made change in capacitance values Conditions. Added Note 3 to Table www.xilinx.com 1-800-255-7778 Table 2. and T to 250 ns in the tables on HOE HCE DC Characteristics Over 1. Other minor edits. 21 ...