XC18Vxxx Xilinx, XC18Vxxx Datasheet - Page 10

• Manufacturer Part Number: XC18Vxxx
• Description: In-System Programmable Configuration PROMs
• Manufacturer: Xilinx

XC18V00 Series In-System Programmable Configuration PROMs
10
Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes
TMS
TMS
TDO
TDO
TCK
TCK
TDI
TDI
J1
J1
1
4
1
4
2
3
2
3
1
2
3
(See Note 2)
1
2
Notes:
For Mode pin connections and DONE pin pullup value, refer to appropriate FPGA data sheet.
For compatible voltages, refer to the appropriate FPGA data sheet.
For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
For compatible voltges, refer to the appropriate FPGA data sheet.
Master/Slave Serial Mode does not require D[1:7] to be connected.
Notes:
VCCO
VCCO
(2)
VCCINT
VCCINT
TDI
TDI
TMS
TCK
TMS
TCK
GND
GND
VCCO
VCCO
VCCINT
VCCINT
Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode
Cascaded
Cascaded
XC18V00
XC18V00
PROM
PROM
OE/RESET
OE/RESET
D[0:7]
CEO
CEO
CLK
CLK
TDO
TDO
CE
CF
CE
CF
(3)
(See Note 2)
D0
VCCO
VCCO
(2)
VCCINT
VCCINT
TDI
TDI
TMS
TCK
TMS
TCK
GND
GND
VCCO
VCCO
VCCINT
VCCINT
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XC18V00
XC18V00
PROM
PROM
First
First
OE/RESET
OE/RESET
D[0:7]
CEO
CEO
CLK
CLK
TDO
TDO
CE
CF
CE
CF
(3)
D0
4.7K
4.7K
VCCO
VCCO
VCCO
VCCO
(1)
(See
Note
1)
(See Note 2)
(2)
(2)
TDI
TMS
TCK
TDI
TMS
TCK
DIN
CCLK
DONE
INIT
PROGRAM
D[0:7]
CCLK
DONE
INIT
PROGRAM
SelectMAP
Virtex-II
Master
Master
Serial/
Xilinx
FPGA
Serial
Xilinx
FPGA
MODE PINS
(3)
MODE PINS
(See Note 1)
DOUT
TDO
TDO
(1)
DS026 (v4.0) June 11, 2003
4.7K
4.7K
Product Specification
TDI
TMS
TCK
TDI
TMS
TCK
DIN
CCLK
**D[0:7]
CCLK
DONE
INIT
PROGRAM
DONE
INIT
PROGRAM
SelectMAP
Virtex-II
Serial/
FPGA
FPGA
Xilinx
Slave
Serial
Xilinx
Slave
MODE PINS
(See Note 1)
MODE PINS
DS026_08_061003
DS026_09_051003
TDO
TDO
R