HIP6017 Intersil Corporation, HIP6017 Datasheet - Page 11

• Manufacturer Part Number: HIP6017
• Description: Advanced PWM and Dual Linear Power Control
• Manufacturer: Intersil Corporation

The modulator transfer function is the small-signal transfer
function of V
gain and the output filter, with a double pole break frequency
at F
simply the input voltage, V
oscillator voltage, V
Modulator Break Frequency Equations
F
The compensation network consists of the error amplifier
internal to the HIP6017 and the impedance networks Z
and Z
provide a closed loop transfer function with an acceptable
0dB crossing frequency (f
Phase margin is the difference between the closed loop
phase at f
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain has
a peak due to the high Q factor of the output filter at F
which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
LC
Z1
Z2
=
LC
=
=
FB
--------------------------------------- -
2
and a zero at F
-----------------------------------
2
------------------------------------------------------ -
2
. The goal of the compensation network is to
0dB
ST
ND
ST
ND
R2 C1
L
1
OUT
R1
1
O
and 180 degrees The equations below relate
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
+
1
C
/V
R3
O
E/A
OSC
. This function is dominated by a DC
ESR
C3
.
2-220
0dB
IN
. The DC gain of the modulator is
F
, divided by the peak-to-peak
ESR
) and adequate phase margin.
F
F
P1
P2
=
---------------------------------------- -
2
=
=
------------------------------------------------------ -
2
-----------------------------------
2
ESR C
1
R
R3 C3
1
2
1
O
C1 C2
--------------------- -
C1
+
C2
LC
P2
IN
LC
,
)
HIP6017
The compensation gain uses external impedance networks
Z
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The linear regulator is internally
compensated and requires an output capacitor that meets
the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and ESL
(effective series inductance) parameters rather than actual
capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
0
and Z
10
(R
20LOG
2
MODULATOR
IN
/R
1
to provide a stable, high bandwidth loop. A
)
GAIN
100
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
F
P1
ESR
(V
100K
IN
20LOG
F
/ V
P2
OSC
OPEN LOOP
ERROR AMP GAIN
1M
)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M