P89LV51RD2 Philips Semiconductors, P89LV51RD2 Datasheet - Page 16

• Manufacturer Part Number: P89LV51RD2
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 6:
9397 750 14101
Product data
Reset source
External reset
Power-on reset
Watchdog reset
Brown-out detect reset
Software reset
Effects of reset sources on bank selection
7.1.5 Watchdog reset
7.1.6 Data RAM memory
7.1.7 Expanded data RAM addressing
SWR bit result
(FCF.1)
0
x
1
the circuit to generate a brown-out interrupt but the CPU still runs until the supplied
voltage returns to the brown-out detection voltage V
brown-out detection is to cause a processor reset.
V
detection circuit will respond.
Brown-out interrupt can be enabled by setting the EBO bit (IEA.3). If EBO bit is set
and a brown-out condition occurs, a brown-out interrupt will be generated to execute
the program at location 004BH. It is required that the EBO bit be cleared by software
after the brown-out interrupt is serviced. Clearing EBO bit when the brown-out
condition is active will properly reset the device. If brown-out interrupt is not enabled,
a brown-out condition will reset the program to resume execution at location 0000H.
A brown-out detect reset will clear the BSEL bit (FCF.0) but will not change the SWR
bit (FCF.1) and therefore will not change the banking of the lower 8 kB of user code
memory space.
Like a brown-out detect reset, the watchdog timer reset will clear the BSEL bit (FCF.0)
but will not change the SWR bit (FCF.1) and therefore will not change the banking of
the lower 8 kB of user code memory space.
The state of the SWR and BSEL bits after different types of resets is shown in
Table
The data RAM has 1024 bytes of internal memory. The device can also address up to
64 kB for external data memory.
The P89LV51RD2 has 1 kB of RAM. See
memory structure.” on page
The device has four sections of internal data memory:
1. The lower 128 bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2. The higher 128 bytes of RAM (80H to FFH) are indirectly addressable.
3. The special function registers (80H to FFH) are directly addressable only.
DD
must stay below V
6. This results in the code memory bank selections as shown.
BSEL bit result
(FCF.0)
0
0
0
Rev. 03 — 11 October 2004
BOD
at least four oscillator clock periods before the brown-out
19.
addresses from 0000h to
1FFFh
Bootcode (in Block 1)
Retains state of SWR bit. If
SWR, BSEL =00 then uses
Bootcode. If SWR, BSEL =
10 then uses user code.
User code (in Block 0)
Figure 6 “Internal and external data
8-bit microcontrollers with 80C51 core
BOD
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
. The default operation for a
P89LV51RD2
addresses above
1FFFh
User code (in Block 0)
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