P89LV51RD2 Philips Semiconductors, P89LV51RD2 Datasheet - Page 43

• Manufacturer Part Number: P89LV51RD2
• Description: 8-bit 80C51 3 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 14101
Product data
Fig 17. SPI master-slave interconnection.
Clock Generator
SPI
An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI
module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock.
Figure 19
Table 30:
Bit addressable; Reset source(s): any reset; Reset value: 00000000B
Table 31:
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
MSB Master LSB
8-bit Shift Register
show the four possible combinations of these two bits.
SPCR - SPI control register (address D5H) bit allocation
SPCR - SPI control register (address D5H) bit description
SPIE
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
7
Rev. 03 — 11 October 2004
SPE
6
Description
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit. When set enables SPI.
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
Master/slave select. 1 = master mode, 0 = slave mode.
Clock polarity. 1 = SCK is high when idle (active LOW), 0 = SCK is
low when idle (active HIGH).
Clock Phase control bit. 1 = shift triggered on the trailing edge of
the clock; 0 = shift triggered on the leading edge of the clock.
SPI Clock Rate Select bit 1. Along with SPR0 controls the SCK
rate of the device when a master. SPR1 and SPR0 have no effect
on the slave. See
SPI Clock Rate Select bit 0. Along with SPR1 controls the SCK
rate of the device when a master. SPR1 and SPR0 have no effect
on the slave. See
SCK
MISO
MOSI
SS
V DD
DORD
5
V SS
MISO
MOSI
SCK
SS
MSTR
Table 32
Table 32
4
8-bit microcontrollers with 80C51 core
below.
below.
CPOL
8-bit Shift Register
MSB Slave LSB
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LV51RD2
CPHA
2
Figure 18
002aaa528
SPR1
1
and
SPR0
43 of 77
0