ST72T311 ST Microelectronics, ST72T311 Datasheet - Page 35

• Manufacturer Part Number: ST72T311
• Description: 8-BIT MCU WITH 8 TO 16K OTP/EPROM
• Manufacturer: ST Microelectronics

4.3 16-BIT TIMER
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals ( input capture ) or generation of up to two out-
put waveforms ( output compare and PWM ).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
4.3.2 Main Features
The Block Diagram is shown in Figure 23.
*Note: Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
Programmable prescaler: f
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
CPU
divided by 2, 4 or 8.
4.3.3 Functional Description
4.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
Alternate Counter Registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 15. The
value in the counter register repeats every
131.072, 262.144 or 524.288 internal processor-
clock cycles depending on the CC1 and CC0 bits.
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MSB).
nificant byte (LSB).
most significant byte (MSB).
least significant byte (LSB).
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