ST72T311 ST Microelectronics, ST72T311 Datasheet - Page 41

• Manufacturer Part Number: ST72T311
• Description: 8-BIT MCU WITH 8 TO 16K OTP/EPROM
• Manufacturer: ST Microelectronics

16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
In this section, the index, i , may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC i E bit if an output is needed then the
– Select the timer clock (CC1-CC0) (see Table
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMP i pins
– Set the OCIE bit to generate an interrupt if it is
When a match is found:
– OCF i bit is set.
– The OCMP i pin takes OLVL i bit value (OCMP i
– A timer interrupt is generated if the OCIE bit is
The OC
ing application can be calculated using the follow-
ing formula:
OCMP i pin is dedicated to the output compare i
function.
15).
after the match occurs.
needed.
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
set in the CR2 register and the I bit is cleared in
the CC register (CC).
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
OC i R
OCIE bit is set
i
R register value required for a specific tim-
f
CPU/(CC1.CC0)
i
R value to 8000h.
MS Byte
OC i HR
).
LS Byte
OC i LR
Where:
f
PRESC
Clearing the output compare interrupt request is
done by:
1. Reading the SR register while the OCF i bit is
2. An access (read or write) to the OC i LR register.
The following procedure is recommended to pre-
vent the OCF i bit from being set between the time
it is read and the write to the OC
– Write to the OC i HR register (further compares
– Read the SR register (first step of the clearance
– Write to the OC i LR register (enables the output
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the clock is divided by 2, OCF i and
4. The output compare functions can be used both
5. The value in the 16-bit OC
CPU
t
are inhibited).
of the OCF i bit, which may be already set).
compare function and clears the OCF i bit).
set.
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see Figure 30, on
page 43). This behaviour is the same in OPM
or PWM mode.
When the clock is divided by 4, 8 or in external
clock mode, OCF i and OCMP i are set while the
counter value equals the OC i R register value
plus 1 (see Figure 31, on page 43).
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
= Desired output compare period (in sec-
= Internal clock frequency
= Timer prescaler factor (2, 4 or 8 de-
onds)
pending on CC1-CC0 bits, see Table
15)
OC i R =
ST72E311 ST72T311
PRESC
t
*
i
R register and the
f
CPU
i
R register:
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