MC9S12D64 Motorola, MC9S12D64 Datasheet - Page 108

• Manufacturer Part Number: MC9S12D64
• Description: MC9S12DJ64 Device User Guide V01.17
• Manufacturer: Motorola

MC9S12DJ64 Device User Guide — V01.17
The phase detector relationship is given by:
i
The loop bandwidth f
typical values are 50. = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
The capacitance C
The capacitance C
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock f
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
ch
C
108
=10kHz:
is the current in tracking mode.
R
=
C
2
---------------------------- -
s
p
s
can now be calculated as:
should be chosen in the range of:
C
f
=
C
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
K
n
<
--------------------- -
K
n f
2
------------------------------------------
C
=
f
C
s
C
=
f
------------ -
VCO
2
f
2
20 C
ref
–
R
= 2* *50*10kHz/(316.7Hz/ )=9.9k =~10k
+
ref
i
ch
is measured and input voltage to the VCO is adjusted
=
1
0.516
-------------- -
f
f
C
ref
p
+
2
K
R
V
2
C
;
synr
s
----- -
10
1
=
10
0.9
+
= 316.7Hz/
1
f
C
f
C
C
p
<
= 5.19nF =~ 4.7nF
< 25kHz
= 470pF
= 50
------------- -
4 10
f
ref
;
=
0.9
cmp
, the