ispPAC10-01PI Lattice Semiconductor, ispPAC10-01PI Datasheet - Page 18

• Manufacturer Part Number: ispPAC10-01PI
• Description: In-System Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor

Electronic Security
An electronic security “fuse” (ESF) bit is provided in every
ispPAC10 device to prevent unauthorized readout of the
E
prevents further access to the functional user bits in the
device. This cell can only be erased by reprogramming
the device, so the original configuration can not be
examined once programmed. Usage of this feature is
optional.
Production Programming Support
Once a final configuration is determined, an ASCII format
JEDEC file is created using the PAC-Designer software.
Parts can then be ordered through the usual supply
channels with the user’s specific configuration already
preloaded into the parts. By virtue of its standard inter-
face, compatibility is maintained with existing production
programming equipment giving customers a wide degree
of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispPAC10 Design Kit is an engineer-
ing prototype board that is connected to the parallel port
of a PC. It demonstrates proper layout techniques for the
Figure 14. Configuring the ispPAC10 “In-System” from a PC Parallel Port
In-System Programmability
2
CMOS user bit patterns. Once programmed, this cell
PAC-Designer
Software
18
ispPAC10 and can be used in real time to check circuit
operation as part of the design process. Input and output
connections as well as a “breadboard” circuit area are
provided to speed debugging of the circuit.
Serial Port Programming Interface
Communication with the ispPAC10 is facilitated via an
IEEE 1149.1 test access port (TAP). It is used by the
ispPAC10 as a serial programming interface, and not for
boundary scan test purposes. There are no boundary
scan logic cells in the ispPAC10 architecture. This does
not prevent the ispPAC10 from functioning correctly,
however, when placed in a valid serial chain with other
IEEE 1149.1 compliant devices.
A brief description of the ispPAC10 serial interface fol-
lows. For complete details of the reference specification,
refer to the publication, Standard Test Access Port and
Boundary-Scan Architecture, IEEE Standard 1149.1-
1990 (which now includes IEEE Standard 1149.1a-1993).
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Specifications ispPAC10
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ispPAC10
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