ispPAC10-01PI Lattice Semiconductor, ispPAC10-01PI Datasheet - Page 20

• Manufacturer Part Number: ispPAC10-01PI
• Description: In-System Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor

tion. This, in conjunction with mandated bit codes, allows
a “blind” interrogation of any device in a compliant IEEE
1149.1 serial chain.
From the Capture state, the TAP transitions to either the
Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test data or status information can
be shifted out or new data shifted in. Following the Shift
state, the TAP either returns to the Run-Test/Idle state
via the Exit1 and Update states or enters the Pause state
via Exit1. The Pause state is used to temporarily suspend
the shifting of data through either the Data or Instruction
Register while an external operation is performed. From
the Pause state, shifting can resume by reentering the
Shift state via the Exit2 state or be terminated by entering
the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR
operation, the next entry into Run-Test/Idle initiates the
test mode (steady state = test). This is when the device
is actually programmed, erased or verified. All other
instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also man-
dates the inclusion of certain instructions. It outlines the
Figure 16. Test Access Port (TAP) Contoller State Diagram
IEEE Standard 1149.1 Interface (Continued)
0
1
Test-Logic-Rst
Run-Test/Idle
Note: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
0
1
1
0
Select-DR-Scan
1
Capture-DR
Update-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
0
0
1
0
1
1
20
0
function of three required and six optional instructions.
Any additional instructions are left exclusively for the
manufacturer to determine. The instruction word length is
not mandated other than to be a minimum of 2 bits, with
only the BYPASS and EXTEST instruction code patterns
being specifically called out (all ones and all zeroes
respectively). The ispPAC10 contains the required mini-
mum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary
instructions that allow the device to be configured and
verified. For ispPAC10, the instruction word length is 5
bits. All ispPAC10 instructions available to users are
shown in Table 2.
BYPASS is one of the three required instructions. It
selects the Bypass Register to be connected between
TDI and TDO and allows serial data to be transferred
through the device without affecting the operation of the
ispPAC10. The bit code of this instruction is defined to be
all ones by the IEEE 1149.1 standard.
The required SAMPLE/PRELOAD instruction dictates the
Boundary-Scan Register be connected between TDI and
TDO. The ispPAC10 has no boundary-scan register, so
for compatibility it defaults to the BYPASS mode when-
ever this instruction is received. The bit code for this
instruction is defined by Lattice as shown in Table 2.
1
1
0
0
Specifications ispPAC10
1
0
Select-IR-Scan
1
Capture-IR
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
0
0
1
0
1
1
0
1
1
0
0