ISPLSI2128VE Lattice Semiconductor, ISPLSI2128VE Datasheet
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ISPLSI2128VE
Manufacturer Part Number
ISPLSI2128VE
Description
3.3V In-System Programmable SuperFAST High Density PLD
Manufacturer
Lattice Semiconductor
Datasheet
1.ISPLSI2128VE.pdf
(19 pages)
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Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
• SuperFAST HIGH DENSITY IN-SYSTEM
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
2128ve_08
Features
PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
— Interfaces with Standard 5V TTL Devices
—
—
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 3.3V In-System Programmability (ISP™) Using
— Open-Drain Output Option for Flexible Bus Interface
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
Machines, Address Decoders, etc.
with ispLSI 2128V Devices
f
t
Boundary Scan Test Access Port (TAP)
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
Market and Improved Product Quality
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 250MHz Maximum Operating Frequency
pd = 4.0ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2128VE is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2128VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2128VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram*
Description
*128 I/O Version Shown
A0
A1
A2
A3
A4
A5
A6
A7
D7
B0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
SuperFAST™ High Density PLD
ispLSI
D6
B1
3.3V In-System Programmable
Global Routing Pool (GRP)
D5
B2
D4
B3
Logic
Array
Output Routing Pool (ORP)
D3
B4
Output Routing Pool (ORP)
®
D
D
D
D
D2
B5
Q
Q
Q
Q
2128VE
D1
B6
September 2000
GLB
D0
B7
C7
C6
C5
C4
C3
C2
C1
C0
0139A/2128VE