HN58X25128I Renesas Technology, HN58X25128I Datasheet
HN58X25128I
Related parts for HN58X25128I
HN58X25128I Summary of contents
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... The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination ...
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... HN58X25128I/HN58X25256I 128k EEPROM (16-kword × 8-bit) 256k EEPROM (32-kword × 8-bit) Electrically Erasable and Programmable Read Only Memory Description HN58X25xxx Series is the Serial Peripheral Interface (SPI) EEPROM (Electrically Erasable and Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 64-byte page programming function to make it’ ...
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... HN58X25128I/HN58X25256I • Small size packages: SOP-8pin and TSSOP-14pin • Shipping tape and reel TSSOP-14pin : 2,000 IC/reel SOP-8pin : 2,500 IC/reel • Temperature range: −40 to +85 °C Ordering Information Type No. Internal organization 128-kbit (16834 × 8-bit) HN58X25128FPI 256-kbit (32768 × 8-bit) HN58X25256FPI 128-kbit (16834 × ...
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... SS (Top view) Pin Description Pin name Function C Serial clock D Serial data input Q Serial data output S Chip select W Write protect HOLD Hold V Supply voltage CC V Ground SS HN58X25128I/HN58X25256I HOLD 14-pin TSSOP HOLD 2 13 ...
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... HN58X25128I/HN58X25256I Block Diagram HOLD D Q Rev.0.0, Nov. 2002, page High voltage generator Memory array Y-select & Sense amp. Serial-parallel converter ...
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... V –0 7 –0.5* IN Topr –40 to +85 Tstg –65 to +125 + 1 Symbol Min V 1 × 0 –0.3* IL Topr –40 HN58X25128I/HN58X25256I Unit +7.0* V °C °C Typ Max Unit 5 × 0 +85 °C ...
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... HN58X25128I/HN58X25256I DC Characteristics Parameter Input leakage current Output leakage current V current Standby CC Active Output voltage Rev.0.0, Nov. 2002, page Symbol Min Max I — — — — 5 CC1 I — 5 CC2 V — 0.4 OL1 V — 0.4 OL2 × 0 — OH1 CC × 0.8 ...
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... Input pules levels: V × 0 V × 0 • Input rise and fall time: ≤ • Input and output timing reference levels: V • Output reference levels • Output load: 100 pF × 0.3, V × 0 × 0.5 HN58X25128I/HN58X25256I Rev.0.0, Nov. 2002, page ...
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... HN58X25128I/HN58X25256I Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not ...
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... Output hold time Output rise time Output fall time HOLD high to output low-Z HOLD low to output low-Z Write time + t ≥ 1/f Notes Value guaranteed by characterization, not 100% tested in production. HN58X25128I/HN58X25256I (Ta = −40 to +85°C, V Symbol Alt Min f f — C SCK t t 100 ...
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... HN58X25128I/HN58X25256I Timing Waveforms Serial Input Timing 5 t CHSL C t DVCH D High Impedance Q Hold Timing HOLD Rev.0.0, Nov. 2002, page SLCH t t CLCH CHDX MSB IN t HLCH t CHHL t CHHH t HLQZ t SHSL CHSH t SHCH t CHCL LSB IN t HHCH t HHQX ...
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... Output Timing 5 C ADDR D LSB IN t CLQV t CLQX Q HN58X25128I/HN58X25256I CLQV t CLQX t SHQZ LSB OUT t QLQH t QHQL Rev.0.0, Nov. 2002, page ...
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... HN58X25128I/HN58X25256I Pin Function Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits. Instructions Each instruction starts with a single-byte code, as summarized in the following table . If an invalid instruction is sent (one not contained in the following table), the device automatically deselects itself. HN58X25128I/HN58X25256I BP1 ...
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... HN58X25128I/HN58X25256I Instruction Set Instruction WREN WRDI RDSR WRSR READ WRITE Write Enable (WREN): The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D) ...
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... The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion Write Disable (WRDI) Sequence HN58X25128I/HN58X25256I ...
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... HN58X25128I/HN58X25256I Read Status Register(RDSR): The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are frozen at their current values just before the start of the execution of the Write Status Register (WRSR) instruction. The new, updated values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. HN58X25128I/HN58X25256I Rev.0.0, Nov. 2002, page ...
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... HN58X25128I/HN58X25256I Write Status Register (WRSR) Sequence Read from Memory Array (READ): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (Q) ...
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... HN58X25128I/HN58X25256I 16-Bit Address High-Z HN58X25256I A14 Data Out 1 Data Out HN58X25128I A13 to A0 Rev.0.0, Nov. 2002, page ...
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... HN58X25128I/HN58X25256I The instruction is not accepted, and is not executed, under the following conditions: If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) Write cycle is already in progress If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits. ...
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... Address High Data Byte High-Z HN58X25128I/HN58X25256I Data Byte Data Byte Rev.0.0, Nov. 2002, page ...
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... None 0 1 Upper quarter 1 0 Upper half 1 1 Whole memory Rev.0.0, Nov. 2002, page Array addresses protected HN58X25256I HN58X25128I None None 6000h − 7FFFh 3000h − 3FFFh 4000h − 7FFFh 2000h − 3FFFh 0000h − 7FFFh 0000h − 3FFFh ...
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... The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being low. The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C) being low. HN58X25128I/HN58X25256I Memory protect Write protection of the status register ...
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... HN58X25128I/HN58X25256I Hold Condition Activation C HOLD Notes Data Protection at V On/Off CC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger When V CC and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • ...
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... Base material dimension 4. 6.02 ± 0.18 0.69 Max 0.60 0.10 0.25 M Hitachi Code JEDEC JEITA Mass (reference value) HN58X25128I/HN58X25256I As of July, 2002 Unit: mm 1.06 0 ˚ – 8 ˚ + 0.289 – 0.194 FP-8DB — — 0.08 g Rev.0.0, Nov. 2002, page ...
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... HN58X25128I/HN58X25256I HN58X25128TI/HN58X25256TI (TTP-14D) 5.00 5.30 Max 14 1 +0.08 *0.22 –0.07 0.20 ± 0.06 0.83 Max *Dimension including the plating thickness Base material dimension Rev.0.0, Nov. 2002, page 0.65 0.13 M 6.40 ± 0.20 0.10 Hitachi Code JEDEC JEITA Mass (reference value July, 2002 Unit: mm 1.0 0˚ – 8˚ 0.50 ± 0.10 TTP-14D — ...
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... Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89 HN58X25128I/HN58X25256I Hitachi Asia Ltd. Hitachi Asia (Hong Kong) Ltd. Hitachi Tower Group III (Electronic Components) 16 Collyer Quay #20-00 7/F., North Tower Singapore 049318 World Finance Centre, Tel : < ...