HN58X25128I Renesas Technology, HN58X25128I Datasheet - Page 21

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HN58X25128I

Manufacturer Part Number
HN58X25128I
Description
(HN58X25128I / HN58X25256I) EEPROM
Manufacturer
Renesas Technology
Datasheet
Read from Memory Array (READ) Sequence
Note:
Address Range Bits
Device
Address bits
Notes: 1. b15 is don’t care on the HN58X25256
Write to Memory Array (WRITE):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The
bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case
of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the
instruction is being used to write a single byte. The self-timed Write cycle starts, and continues for a period
t
If, though, chip select (S) continues to be driven low, as shown in the following figure, the next byte of the
input data is shifted in, so that more than a single byte, starting from the given address towards the end of the
same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are
incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address
counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming
data. (The page size of these device is 64 bytes).
WC
9
Q
C
D
5
(as specified in AC Characteristics). At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
2. b15 and b14 are don’t care on the HN58X25128
1. Depending on the memory size, as shown in the following table, the most significant address bits
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
are don’t care.
0
1
2
Instruction
3
4
HN58X25256I
A14 to A0
5
High-Z
6
7
15
8
14
9 10
16-Bit Address
13
20 21 22 23 24 25 26 27 28 29 30 31
3
2
1
HN58X25128I/HN58X25256I
0
7
6
Rev.0.0, Nov. 2002, page 19 of 27
5
HN58X25128I
A13 to A0
Data Out 1
4
3
2
1
0
7
Data Out 2

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