HN58X25128I Renesas Technology, HN58X25128I Datasheet - Page 22
HN58X25128I
Manufacturer Part Number
HN58X25128I
Description
(HN58X25128I / HN58X25256I) EEPROM
Manufacturer
Renesas Technology
Datasheet
1.HN58X25128I.pdf
(29 pages)
- Current page: 22 of 29
- Download datasheet (247Kb)
HN58X25128I/HN58X25256I
The instruction is not accepted, and is not executed, under the following conditions:
Byte Write (WRITE) Sequence (1 Byte)
Note:
Rev.0.0, Nov. 2002, page 20 of 27
9
Q
C
D
If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just
If a Write cycle is already in progress
If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
5
before)
1. Depending on the memory size, as shown in Address Range Bits table, the most significant
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
address bits are don’t care.
0
1
2
Instruction
3
4
5
6
7
15
8
14
9 10
16-Bit Address
13
High-Z
20 21 22 23 24 25 26 27 28 29 30 31
3
2
1
0
7
6
5
Data Byte 1
4
3
2
1
0
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