AS7C256 ETC, AS7C256 Datasheet - Page 2

• Manufacturer Part Number: AS7C256
• Description: High Performance 32Kx8 CMOS SRAM
• Manufacturer: ETC

AS7C256
AS7C256L
The AS7C256 is a high performance CMOS 262,144-bit
Static Random Access Memory (SRAM) organized as
32,768 words
tions where fast data access, low power, and simple interfac-
ing are desired.
Equal address access and cycle times (t
10/12/15/20/25/35 ns with output enable access times (t
of 3/3/4/5/6/8 ns are ideal for high performance applica-
tions. A chip enable (CE) input permits easy memory
expansion with multiple-bank memory organizations.
When CE is HIGH the device enters standby mode. The
standard AS7C256 is guaranteed not to exceed 11 mW
power consumption in standby mode; the L version is guar-
anteed not to exceed 2.75 mW, and typically requires only
500 W. The L version also offers 2.0V data retention, with
maximum power consumption in this mode of 300 W.
Parameter
CE
Voltage on Any Pin Relative to GND
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
DC Output Current
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
H
L
L
L
Key: X = Don’t Care, L = LOW, H = HIGH
FUNCTIONAL DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
.
8 bits. It is designed for memory applica-
WE
X
H
H
L
OE
X
H
L
X
AA
, t
RC
, t
WC
) of
OE
Symbol
Data
)
V
P
T
T
I
High Z
High Z
D
D
out
D
stg
bias
t
out
in
2
A write cycle is accomplished by asserting chip enable (CE)
and write enable (WE) LOW. Data on the input pins
I/O0-I/O7 is written on the rising edge of WE (write cycle 1)
or CE (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been
disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE)
and output enable (OE) LOW, with write enable (WE)
HIGH. The chip drives I/O pins with the data word refer-
enced by the input address. When chip enable or output
enable is HIGH, or write enable is LOW, output drivers stay
in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and opera-
tion is from a single 5V supply. The AS7C256 is packaged
in all high volume industry standard packages.
Min
–0.5
–
–55
–10
–
Max
Mode
+7.0
1.0
+150
+85
20
Standby (I
Output Disable
Read
Write
SB
, I
SB1
)
Unit
V
W
o
o
mA
C
C