BS62LV4001DC Brilliance Semiconductor, BS62LV4001DC Datasheet

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BS62LV4001DC

Manufacturer Part Number
BS62LV4001DC
Description
Low Power/Voltage CMOS SRAM 512K X 8 bit
Manufacturer
Brilliance Semiconductor
Datasheet
R0201-BS62LV4001
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Low power consumption
• High speed access time :
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
Vcc = 3.0V
Vcc = 5.0V
FEATURES
PRODUCT FAMILY
-70
-10
VC
A11
A13
A17
A15
A18
A16
A14
A12
WE
BSI
A9
A8
A7
A6
A5
A4
C
GND
DQ0
DQ1
DQ2
100ns (Max.) at Vcc = 3.0V
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
70ns (Max.) at Vcc = 3.0V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C-grade: 20mA (Max.) operating current
C-grade: 45mA (Max.) operation current
I -grade: 25mA (Max.) operating current
0.25uA (Typ.) CMOS standby current
I -grade: 50mA (Max.) operating current
1.5uA (Typ.) CMOS standby current
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4001SC
BS62LV4001SI
BS62LV4001EC
BS62LV4001EI
BS62LV4001PC
BS62LV4001PI
BS62LV4001TC
BS62LV4001STC
BS62LV4001TI
BS62LV4001STI
Low Power/Voltage CMOS SRAM
512K X 8 bit
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
. reserves the right to modify document contents without notice.
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
The BS62LV4001 is a high performance, low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with maximum access time of 70/ 100ns
in 3.0V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62LV4001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4001 is available in DICE form, JEDEC standard 32 pin
SOP, 32 pin TSOPII, 32 pin TSOP and 32 pin Small SOP.
1
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
A13
A17
A15
A18
A16
A14
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vdd
Gnd
A7
A6
A5
A4
WE
CE
OE
Address
Buffer
Input
8
Control
8
22
Output
Buffer
Buffer
Data
Input
Data
Decoder
Row
8
2048
8
BS62LV4001
A11 A9 A8 A3 A2 A1 A0 A10
Address Input Buffer
Column Decoder
Memory Array
2048 X 2048
Sense Amp
Write Driver
Column I/O
2048
256
16
Revision 2.5
April 2002

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BS62LV4001DC Summary of contents

Page 1

... Brilliance Semiconductor Inc R0201-BS62LV4001 GENERAL DESCRIPTION The BS62LV4001 is a high performance, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum access time of 70/ 100ns in 3 ...

Page 2

BSI PIN DESCRIPTIONS Name A0-A18 Address Input CE Chip Enable Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports Vcc Gnd TRUTH TABLE MODE WE Not selected X Output Disabled H Read H Write L ABSOLUTE ...

Page 3

BSI DC ELECTRICAL CHARACTERISTICS PARAMETER PARAMETER NAME Guaranteed Input Low V IL (2) Voltage Guaranteed Input High V IH (2) Voltage I Input Leakage Current IL I Output Leakage Current OL V Output Low Voltage OL V Output High Voltage ...

Page 4

BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level AC TEST LOADS AND WAVEFORMS Ω 1269 3.3V OUTPUT 100PF INCLUDING Ω 1404 JIG AND SCOPE FIGURE 1A THEVENIN EQUIVALENT 667 OUTPUT ...

Page 5

BSI SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 ADDRESS D OUT (1,3,4) READ CYCLE2 CE D OUT (1,4) READ CYCLE3 ADDRESS OUT NOTES high in read Cycle. 2. Device is continuously selected when CE ...

Page 6

BSI AC ELECTRICAL CHARACTERISTICS WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME t t AVAX E1LWH AVW AVWH WLWH WHAX WLOZ WHZ ...

Page 7

BSI (1,6) WRITE CYCLE2 ADDRESS OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals ...

Page 8

BSI ORDERING INFORMATION BS62LV4001 PACKAGE DIMENSIONS SOP -32 R0201-BS62LV4001 WITH PLATING BASE METAL SECTION A-A 8 BS62LV4001 SPEED 70: 70ns 10: 100ns GRADE + ...

Page 9

BSI PACKAGE DIMENSIONS (continued) TSOP2 - 32 TSOP - 32 R0201-BS62LV4001 9 BS62LV4001 Revision 2.5 April 2002 ...

Page 10

BSI PACKAGE DIMENSIONS (continued) STSOP - 32 PDIP - 32 R0201-BS62LV4001 10 BS62LV4001 Revision 2.5 April 2002 ...

Page 11

BSI REVISION HISTORY Revision Description 2.2 2001 Data Sheet release 2.3 Modify Standby Current (Typ. and Max.) 2.4 To add DICE form 2.5 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 25uA to 50uA. R0201-BS62LV4001 Date Apr. 15, 2001 Jun. ...

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