73K224BL-IGT ETC, 73K224BL-IGT Datasheet

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... PLCC and 44-Lead TQFP package. The 73K224BL operates from a single +5 V supply for low power consumption. The 73K224BL is designed to appear to the systems designer as a microprocessor peripheral, and will easily interface with popular single-chip micro- processors (80C51 typical) for control of modem functions through its 8-bit multiplexed address/data bus or via an optional serial control bus ...

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... V) TTL and CMOS compatible inputs and outputs DPSK MODULATOR/DEMODULATOR The 73K224BL modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A/V.22 standards. The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line ...

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... These registers are addressed multiplexed address lines (latched by ALE) and appear to a control microprocessor as seven consecutive registers are read/write memory. The detect and ID registers are read only and cannot be modified except by parameters. 3 73K224BL with the AD0, AD1, and memory locations. Six control modem ...

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... Single-Chip Modem w/ Integrated Hybrid SERIAL CONTROL INTERFACE MODE The serial Command mode allows access to the 73K224BL control and status registers via a serial control port. In this mode the AD0, AD1, and AD2 lines provide register addresses for data passed through the AD7 (DATA) pin under control of the RD and WR lines ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid TYPE DESCRIPTION I System ground I Power supply input ±10% (73K224BL). Bypass with 0.1 and 22 µF capacitors to GND internally generated reference voltage. Bypass with 0.1 µF capacitor to ground. I Chip current reference. Sets bias current for op-amps. The ...

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... RD pin. RD low outputs data. RD high inputs data. I READ: A low on this input informs the 73K224BL that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register ...

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... TRANSMIT DATA INPUT: Serial data for transmission is applied on this pin. In synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud) no clocking is necessary. DPSK data must be 1200/600 bit/s +1%, -2.5% or +2.3%, -2 extended over speed mode. 7 73K224BL ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid PIN DESCRIPTION (continued) ANALOG INTERFACE AND OSCILLATOR NAME PIN RXA 32 TXA1 / TXA2 XTL1 / XTL2 TYPE DESCRIPTION I Received modulated analog signal input from the telephone line interface. O Transmit Analog (differential outputs): These pins provide the analog output signals to be transmitted to the telephone line ...

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... BOOST 1=OH OPEN DRAIN DRIVER PULLING LOW TXD RX UNSCR. 0 SOURCE CLOCK DATA OUTPUTS 0=TXD PIN UNSCR. 1=TXALT BIT DATA 73K224BL TRANSMIT TRANSMIT ORIGINATE/ MODE ENABLE ANSWER ANSWER 0 = DISABLE 1 = ORIGINATE TXA OUTPUT 1 = ENABLE TXA OUTPUT TEST TEST RESET MODE ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid CONTROL REGISTER 0 CR0 D7 D6 ADDR MODUL. MODUL. MODUL. 000 OPTION TYPE 1 TYPE 0 BIT NAME D0 Answer/ Originate D1 Transmit Enable D5,D4 Transmit D3,D2 Mode D6,D5 Modulation Type TRANSMIT TRANSMIT MODE 2 MODE 1 CONDITION DESCRIPTION 0 Selects answer mode (transmit in high band, receive in low band) ...

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... CR3 bit D2. The output of the clock pin will be set to the crystal frequency. 0 Selects 11.0592 MHz crystal echo output at CLK pin 1 Selects 16 times the data rate output at CLK pin in DPSK/QAM modes only. 11 73K224BL D2 D1 TRANSMIT TRANSMIT ANSWER/ MODE 0 ENABLE ORIGINATE ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid CONTROL REGISTER 1 (continued) CR1 D7 D6 ADDR TRANSMIT TRANSMIT 001 PATTERN PATTERN 1 0 BIT NAME D4 Bypass Scrambler D5 Enable Detect Interrupt D6, D7 Transmit Pattern DETECT REGISTER ADDR RECEIVE S1 010 LEVEL PATTERN INDICATOR DETECT BIT ...

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... S1 pattern is defined as a double di-bit (001100..) unscrambled 1200 bit/s DPSK signal. Pattern must be aligned with baud clock to be detected. 0 Received signal level below threshold, (typical -25 dBm0); can use receive gain boost (+18 dB). 1 Received signal above threshold. 13 73K224BL ANSWER CALL SIGNAL TONES PROG. ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid TONE REGISTER ADDR RXD TRANSMIT 011 OUTPUT GUARD CONTROL TONE BIT NAME D0 DTMF 0/ Answer/ Guard Tone D1 DTMF 1/ Extended Overspeed D2 DTMF 2/ 4 Wire FDX D5 D4 TRANSMIT TRANSMIT DTMF 3 ANSWER DTMF TONE CONDITION DESCRIPTION ...

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... Disable DTMF. 1 Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. 15 73K224BL DTMF 2/ DTMF 1/ 4-WIRE EXTENDED FDX OVER- SPEED TONES LOW 697 697 697 770 ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid TONE REGISTER (continued ADDR RXD TRANSMIT 011 OUTPUT GUARD CONTROL TONE BIT NAME D5 Transmit Answer Tone D6 Transmit Guard Tone D7 RXD Output Control TRANSMIT TRANSMIT DTMF 3 ANSWER DTMF TONE CONDITION DESCRIPTION interacts with bits D4 and D0 as shown ...

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... The DSP decodes unscrambled mark, answer tone and call progress tones. 0 Normal CR3 access. 1 Setting this bit and addressing CR3 allows access to the special register (see the special register for details). 0 Only write zero to this bit. 17 73K224BL RESET RESET RESET RESET RESET RESET ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid CONTROL REGISTER 3 CR3 D7 D6 ADDR TXDALT TRI-STATE 101 TX/RXCLK BIT NAME D3, D2, Transmit Attenuator D1,D0 D4 Receive Gain Boost Tri-state TXCLK/RXCLK D7 TXDALT RECEIVE TRANSMIT BOOST ATTEN. 3 ENABLE CONDITION DESCRIPTION ...

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... NOTE: This register is "mapped" and is accessed by setting CR2 bit one and addressing CR3. This register provides functions to the 73K224BL user that are not necessary in normal communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be returned to a zero. ...

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... D7 D6 ADDR ID ID 110 BIT NAME D7, D6, D5 CONDITION DESCRIPTION Indicates Device 73K212L, 73K321L or 73K322L 73K221L or 73K302L 73K222L or 73K222BL 73K224L, 73K224BL 73K324L, 73K324BL ...

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... NOTE 1: Minimum for optimized system layout; may require higher values for noisy environments. V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid RATING 7 V -65 to 150° C 235° C -0.3 to VDD + 0.3 V MIN 4.5 -40 -0.01 0.1 1.8 0.1 0 73K224BL NOM MAX UNIT 5 5.5 V +85 C +0.01 % µF 2 2.2 µF µF µF 40 ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid DC ELECTRICAL CHARACTERISTICS (TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.) PARAMETER CONDITION IDD, Supply Current CLK = 11.0592 MHz ISET Resistor = 2 M IDD1, Active Operating with crystal oscillator, IDD2, Idle < capacitive load on CLK pin ...

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... Hz test signal Delay time -70 dBm0 to -30 dBm0 step Hold time -30 dBm0 to -70 dBm0 step V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid (continued) MIN 35 -11.5 -0.31 -11.5 -10 -15 -17 -11.5 -0.03 - -43 -34 23 73K224BL NOM MAX UNIT dB -10 -9 dBm0 +0.20 % -10 -9 dBm0 -45 dB +10 % +15 % +17 % -10 -9 dBm0 ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid DYNAMIC CHARACTERISTICS AND TIMING PARAMETER CONDITION Carrier Detect Receive gain = On for lower input level measurements Threshold All modes Hysteresis All modes Delay Time FSK 70 dBm0 to -6 dBm0 Change at input 70 dBm0 to -40 dBm0 Change at input ...

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... Guard Tone Generator Tone Accuracy 550 Hz 1800 Hz Tone Level 550 Hz (Below QAM/DPSK Output) 1800 Hz Harmonic Distortion 550 Hz (700 to 2900 Hz) 1800 Hz V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid (continued) MIN -22 -0.15 -0.02 -4.5 -7.5 25 73K224BL NOM MAX UNIT -6 dBm0 +0.15 dB 1.5 mVrms ±5 Hz +0.02 % +1.2 % -0.8 -3.0 -1.5 dB -6.1 -4.5 dB -50 ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid DYNAMIC CHARACTERISTICS AND TIMING PARAMETER CONDITION TIMING * (Refer to Timing Diagrams) CS /Address setup before ALE Low TAL CS CS TLA AD0-AD7 Address hold after ALE Low ALE Low to RD/WR Low TLC RD/WR Control to ALE High TCL Data out from RD Low ...

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... FIGURE 4: Write Timing Diagram (Serial Control Mode) V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid TLC TRW TCL TLA TRD TRDF READ DATA TCKD 73K224BL TLC TWW TWD TDW ADDRESS WRITE DATA TCKW TAC ADDRESS TWH TRDF ...

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... A typical DAA arrangement is shown in Figure 5. This diagram is for reference only and does not represent a production-ready modem design. The 73K224BL is available with two control interface versions: one for a parallel multiplexed RING DETECT TX DATA RX DATA 11.0592 ...

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... APPLICATIONS INFORMATION DIRECT ACCESS ARRANGEMENT (DAA) The DAA (Direct Access Arrangement) required for the 73K224BL consists of an impedance matching resistor, telecom coupling transformer, and ring detection and fault protection circuitry. The transformer specifications must comply with the impedance of the country in which the modem ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces ...

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... BER vs S/N-DPSK LOW BAND -2 10 LOW BAND RECEIVE -30 dBm DPSK OPERATION 1200 BIT 3002 -4 10 C1, C2, FLAT - SIGNAL TO NOISE (dB) 73K224BL BER VS S/N-QAM-LOW BAND -2 10 HIGH BAND RECEIVE -30 dBm QAM OPERATION 2400 BIT FLAT -4 10 ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid MECHANICAL SPECIFICATIONS 32-Lead PLCC 0.453 (11.51) 0.449 (11.40) PIN NO. 1 IDENT. 0.595 (15.11) 0.585 (14.86) 0.495 (12.57) 0.485 (12.32) 44-Lead TQFP 1 0.09 (0.035) 1.35 (0.053) 0.20 (0.008) 1.45 (0.057) 0.140 (3.56) 0.123 (3.12) 0.095 (2.41) 0.078 (1.98) 0.553 (14.05) 0.549 (13.94) 0.300 REF (7.62 REF) 0.430 (10.92) 16.0 BSC (0.630) INDEX 14.0 BSC (0.552) ...

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... V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid ISET OH 27 RXCLK 26 RXD 25 24 TXD EXCLK TXCLK ORDER NUMBER 73K224BL-IH 73K224BL-IGT 33 73K224BL CAUTION: Use handling procedures necessary for a static sensitive component. 44-Lead TQFP 73K224BL-IGT PACKAGING MARK 73K224BL-IH 73L224BL-IGT 04/24/00 - rev. E ...