ZL50120 Zarlink, ZL50120 Datasheet - Page 26

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

4.0
The following key applies to all tables:
4.1
All TDM Interface signals are 5 V tolerant.
All TDM Interface outputs are high impedance while System Reset is LOW.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
4.1.1
There are three interfaces possible among the ZL5011x.
The ZL50117/20 supports four TDM ports [3:0] at 2 Mbps, or one TDM port [0] at 8 Mbps or one unstructured TDM
port [0] for J2/E3/T3/STS-1.
The ZL50116/19 supports two TDM ports [1:0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 64 DS0).
The ZL50115/18 supports one TDM port [0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 32 DS0)
TDM_STi[3:0]
TDM Interface
External Interface Description
Signal
TDM stream connections
I
O
D
U
T
Input
Output
Internal 100 kΩ pull-down resistor present
Internal 100 kΩ pull-up resistor present
Tri-state Output
I/O
I D
[3]
[2]
[1]
[0]
Table 3 - TDM Interface Stream Pin Definition
M3
N3
R2
U1
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
26
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[3:0]
H.110:
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
stream [0] is used. Stream [0] is used for
unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
TDM_D[3:0]
Description
Data Sheet