ZL50120 Zarlink, ZL50120 Datasheet - Page 31

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

M_MDC
M_MDIO
M0_LINKUP_LED
M0_ACTIVE_LED
M0_GIGABIT_LED
M0_REFCLK
M0_RXCLK
Signal
Signal
OT
I/O
ID/
I/O
I D
I U
O
Table 7 - MII Management Interface Package Ball Definition
O
O
O
Table 8 - MII Port 0 Interface Package Ball Definition
H1
G1
G3
D17
E2
D11
C10
ZL50115/16/17/18/19/20
Package Balls
Package Balls
Zarlink Semiconductor Inc.
MII Port 0
31
MII management data clock. Common for all
four MII ports. It has a minimum period of
400 ns (maximum freq. 2.5 MHz), and is
independent of the TXCLK and RXCLK.
MII management data I/O. Common for all
four MII ports at up to 2.5 MHz. It is
bi-directional between the ZL5011x and the
Ethernet station management entity. Data is
passed synchronously with respect to
M_MDC.
LED drive for MAC 0 to indicate port is linked
up.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 0 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 0 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M0_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M0_RXCLK.
GMII/MII - M0_RXCLK.
Accepts the following frequencies:
125.0 MHz
25.0 MHz
MII
GMII 1 Gbps
Description
Description
100 Mbps
Data Sheet