ZL50120 Zarlink, ZL50120 Datasheet - Page 54

• Manufacturer Part Number: ZL50120
• Description: 32 / 64 / 128 Channel CESoP Processors
• Manufacturer: Zarlink

6.5
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane
requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the
ZL5011x family: UDP, RTP, L2TP, CESoPSN, SAToP and CDP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the
CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a
timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various
protocols to be placed at variable locations within the header.
6.6
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4
and 6) and MPLS.
6.7
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a
packet classifier to determine the destination. When a packet is successfully classified the destination can be the
TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context
it is intended for.
Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM
streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay
across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 µs).
There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. The host’s DMA
controller can be used to retrieve packet data and write it out into the CPU’s own memory.
6.8
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets
received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM
Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output
TDM interface.
When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM
frames as were included in the missing packet. Underrun data can either be the last value played out on that
timeslot, or a pre-programmed value (e.g., 0xFF). If the packet subsequently turns up it is discarded. In this way, the
end-to-end latency through the system is maintained at a constant value.
6.9
The ZL5011x allows native Ethernet traffic received on the customer side Fast Ethernet port to be aggregated with
the CESoP traffic from the TDM interface to the provider side Gigabit Ethernet port. Likewise, traffic from the
provider side Gigabit Ethernet port may be split between CESoP traffic destined towards the TDM interface and
native Ethernet traffic destined towards the customer side Fast Ethernet port. This functionality is achieved by
correctly programming the task manager and packet classifiers for flow 11.
From the provider side Gigabit Ethernet port to the customer side TDM and Fast Ethernet interfaces there is
sufficient internal bandwidth to avoid any prioritization issues. From the customer side TDM and Fast Ethernet
interfaces towards the Gigabit Ethernet ports the TDM CESoP traffic may be sent to a higher priority output queue
(there are four output queues total) than the native Fast Ethernet traffic. In this way the access to the provider side
Gigabit Ethernet port is prioritized for TDM traffic over native Ethernet traffic.
Protocol Engine
Packet Transmission
Packet Reception
TDM Formatter
Ethernet Traffic Aggregation (ZL50118/19/20 only)
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
54
Data Sheet