AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 35

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

Collision—Microcode Interaction
The microprogram uses the time provided by COLLI-
SION JAM, INTERPACKET DELAY, and the backoff
interval to restore the address and byte counts internally
and starts loading the Transmit FIFO in anticipation of
retransmission. It is important that C-LANCE be ready
to transmit when the backoff interval elapses to utilize
the channel properly.
If, during the backoff interval, RENA and CLSN are
never asserted (no wire activity), the C-LANCE does not
re-poll the OWN bit and does not re-read the buffer ad-
dress and byte count in the transmit descriptor before
reloading the transmit data and retransmitting the trans-
mit packet. However, if RENA or CLSN are asserted
during the backoff interval, the C-LANCE must re-poll
the OWN bit and re-read the buffer address and byte
count in the transmit descriptor before starting the DMA
access of the transmit buffer and performing the retry.
Note that the re-polling of the transmit descriptor could
be preceeded by receive DMA operations if an incoming
packet arrives during the backoff interval and an ad-
dress match is detected or when the C-LANCE is in pro-
miscuous mode.
Time Domain Reflectometry
The C-LANCE contains a time domain reflectometry
counter. The TDR counter is ten bits wide. It counts at a
10 MHz rate. It is cleared by the microprogram and
counts upon the assertion of RENA during transmission.
Counting ceases if CLSN becomes true, or RENA goes
inactive. The counter does not wrap around. Once all
ONEs are reached in the counter, the counter value is
held until cleared. The value in the TDR is written into
memory following the transmission of the packet. TDR is
used to determine the location of suspected cable faults.
Heartbeat
During the interpacket gap time following the negation of
TENA, the CLSN input is asserted by some transceivers
as a self-test. If the CLSN input is not asserted within
4 s following the completion of transmission, then the
C-LANCE will set the CERR bit in CSR0. CERR error
will not cause an interrupt to occur (INTR = 0).
Cyclic Redundancy Check (CRC)
The C-LANCE utilizes the 32-bit CRC function as de-
scribed in the IEEE 802.3 standard section 3.2.8 to gen-
erate the Frame Check Sequence (FCS) field. The
C-LANCE requirements for the CRC logic are the
following:
TRANSMISSION – MODE <02> LOOP = 0, MODE
<03> DTCR = 0. The C-LANCE calculates the
CRC from the first bit following the SFD to the last
bit of the data field. The CRC value inverted is ap-
pended onto the transmission in one unbroken bit
stream.
P R E L I M I N A R Y
Am79C90
Loopback
The normal operation of the C-LANCE is as a half-
duplex device. However, to provide an on-line opera-
tional test of the C-LANCE, a pseudo-full duplex mode is
provided. In this mode simultaneous transmission and
reception of a loopback packet are enabled with the fol-
lowing constraints:
Loopback is controlled by bits <06, 03, 02> INTL, DTCR,
and LOOP of the MODE register.
RECEPTION – MODE <02> LOOP = 0. The
C-LANCE performs a check on the input bit stream
from the first bit following the SFD to the last bit in
the frame. The C-LANCE continually samples the
state of the CRC check on framed byte bounda-
ries, and, when the incoming bit stream stops, the
last sample determines the state of the CRC error.
Framing error (FRAM) is not reported if there is no
CRC error.
LOOPBACK – MODE <02> LOOP =1, MODE
<03> DTRC = 0. The C-LANCE generates and
appends the CRC value to the outgoing bit stream
as in Transmission but does not perform the CRC
check of the incoming bit stream.
LOOPBACK – MODE <02> LOOP = 1 MODE
<03> DTRC = 1. C-LANCE performs the CRC
check on the incoming bit stream as in Reception,
but does not generate or append the CRC value to
the outgoing bit stream during transmission.
The packet length must be no longer than
32 bytes, and no shorter than 8 bytes, exclusive of
the CRC.
Serial transmission does not begin until the Trans-
mit FIFO contains the entire output packet.
Moving the input packet from the Receive FIFO to
the memory does not begin until the serial input bit
stream terminates.
CRC may be generated and appended to the out-
put serial bit stream or may be checked on the in-
put serial bit stream. CRC may not be used for
both transmission and reception simultaneously.
In internal loopback, the packets should be ad-
dressed to the node itself.
In external loopback, multicast addressing can be
used only when DTCR = 1 is in the mode register.
In this case, the user needs to append the CRC
bytes.
AMD
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