AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 58

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

5. Backoff Algorithm
A selectable Modified Backoff Algorithm is provided in
the C-LANCE device that can improve throughput in
busy networks. Bit 7 of the Mode register (EMBA bit) is
used to enable the Modified Backoff Algorithm. This bit
is RESERVED in the LANCE device.
With the Modified Backoff Algorithm, counting of the
IFS interval is suspended when receive carrier sense is
detected. The count resumes when receive carrier
sense goes away. This algorithm increases throughput
in large networks with heavy traffic (many collisions). It
can be considered an “adaptive” backoff algorithm.
This mode should only be used in network segments in
which all nodes are using this mode. Otherwise, the
nodes that are using it will be at a disadvantage to
those that are not.
Note: This mode does not conflict with IEEE require-
ments for compliance. The IEEE 802.3 specification
specifies only the minimum amount of time for the
backoff interval. This leaves open the possibility of
backing off more than the minimum, which is precisely
how the Modified Backoff Algorithm works.
The Modified Backoff Algorithm is included as an
option in the MACE™ (Am79C940) and PCnet-ISA
(Am79C960) devices.
6. TX Descriptor Zero Buffer Byte Count Capability
The 12-bit BCNT field in the transmit descriptor of the
LANCE and C-LANCE devices is loaded with the 2’s
complement of the number of bytes that must be trans-
mitted from the buffer. With the 2’s complement repre-
sentation, a simple incrementer is used in the chip to
count through the byte count as bytes are being read
from the transmit buffer. When the 2’s complement
number reaches all 0’s, the count has expired. The
LANCE device does not check for the all 0’s case when
the BCNT field is first loaded from the descriptor.
Hence, the all 0’s case is interpreted by the LANCE de-
vice as a buffer count of 4096 (2
length TX buffers in the LANCE device. In addition, the
LANCE device ignores the upper 4 bits in TMD2, which
are adjacent to the BCNT field. These bits are indicated
as “must be ones” in the LANCE data sheet.
The C-LANCE device actually uses all 16 bits in TMD2
as the BCNT field. Compatibility with the LANCE de-
vice is preserved as long as the upper 4 bits in TMD2
are 1’s, as specified in the LANCE data sheet. The
C-LANCE device checks for the case where all 16 bits
in TMD2 are zero before starting any transmit DMA
from the buffer. If all 16 bits are zero, a zero-length
buffer is assumed, and the C-LANCE device immedi-
ately clears the OWN in the descriptor without starting
any transmit activity on the network. Note that since all
16 bits are checked, compatibility with the LANCE
device is preserved for non-Ethernet-compliant
58
12
), preventing zero-
Am79C90
implementations, which may use buffer lengths of 4096
bytes.
Zero Transmit Buffer Byte Count Capability is included
in the PCnet-ISA device.
7. Interframe Spacing (IFS) Behavior
a. Two-Part Deferral After Transmit: Two-part deferral
.
b. The IEEE 802.3 specifications state that part 1 of
c. IEEE 802.3 specifications state that the Signal
802.3 specification by the IEEE committee. With
two-part deferral, the IFS is divided into two parts,
IFS1 and IFS2. If there is activity on the wire during
IFS1, the IFS counter is reset until the wire is clear
again. The IFS counter is not reset once it enters
IFS2. When the IFS counter expires, the chip will
begin to transmit if it has anything to send.
The specification’s wording for two-part deferral
after transmit is identical to the way that two-part de-
ferral after receive has been worded all along. That
is, the specification specifies that part 1 of the two
parts can be anywhere from 0 to 2/3 of the IFS
(9.6 s). If part 1 = 0 (perfectly legal), it is equivalent
to not implementing two-part deferral at all. Hence,
the LANCE device, which implements two-part de-
ferral after receive but not after transmit, complies
with IEEE specifications. However, implementation
of two-part deferral after both transmit and receive
eliminates a possible scenario where packets can-
not be received (due to very small or 0 IFS) but
there is no indication of this fact through a collision
indication at the transmitter. Therefore, although
this scenario is very rare, the C-LANCE device im-
plements two-part deferral after transmit in addition
to after receive.
two-part deferral can be anywhere from 0 to 2/3 of
the IFS (9.6 s). The LANCE device only imple-
ments two-part deferral after receive, with part
1 = 4.1 s and part 2 = 5.5 s (compliant). The
C-LANCE device implements two-part deferral after
both transmit and receive with part 1 = 6.0 s and
part 2 = 3.6 s. Since the receiver is blinded follow-
ing a transmit for 4.0 s (see below), part 1 of two-
part deferral after a transmit had to be extended be-
yond 4.1 s or else part 1 would effectively be only
from 4.0 s to 4.1 s during the IFS. Hence, in the
C-LANCE device, part 1 of two-part deferral after
transmit was set at 6.0 s and the same value was
used for part 1 following a receive.
Quality Error (SQE) test window should be at least
4.0 s and no more than 8.0 s. The LANCE device
implements a 2- s window, which is not compliant
with this specification. This generally turns out to be
a non-issue because 802.3 also specifies that the
after receive has always been an option in the IEEE
802.3 specification. However, two-part deferral after
transmit was recently added as an option in the