AM79C90 Advanced Micro Devices, AM79C90 Datasheet - Page 6

• Manufacturer Part Number: AM79C90
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: Advanced Micro Devices

The C-LANCE drives these lines as a Bus Master and
as a Bus Slave.
6
CLSN
Collision (Input)
A logical input that indicates that a collision is occurring
on the channel.
CS
Chip Select (Input)
Indicates, when asserted, that the C-LANCE is the
Slave device of the data transfer. CS must be valid
throughout the data portion of the bus cycle. CS must
not be asserted when HLDA is LOW.
DAL00–DAL15
Data/Address Lines (Input/Output, Three-State)
The time multiplexed Address/Data bus. During the ad-
dress portion of a memory transfer, DAL00–DAL15
contains the lower 16 bits of the memory address. The
upper 8 bits of address are contained in A16–A23.
During the data portion of a memory transfer, DAL00–
DAL15 contains the read or write data, depending on
the type of transfer.
DALI
Data/Address Line In (Output, Three-State)
An external bus transceiver control line. DALI is as-
serted when the C-LANCE reads from the DAL lines. It
will be LOW during the data portion of a READ transfer
and remain HIGH for the entire transfer if it is a WRITE.
DALI is driven only when C-LANCE is a Bus Master.
DALO
Data/Address Line Out (Output, Three-State)
An external bus transceiver control line. DALO is as-
serted when the C-LANCE drives the DAL lines. DALO
will be LOW only during the address portion if the trans-
fer is a READ. It will be LOW for the entire transfer if the
transfer is a WRITE. DALO is driven only when
C-LANCE is a Bus Master.
Signal Line
BYTE = L and
DAL00 = L
BYTE = L and
DAL00 = H
BYTE = H and
DAL00 = H
BYTE = H and
DAL00 = L
and BCON = 1
Upper Byte
Lower Byte
BSWP = 0
Illegal
Word
Mode Bits
and BCON = 1
Lower Byte
Upper Byte
BSWP = 1
Illegal
Word
P R E L I M I N A R Y
Am79C90
DAS
Data Strobe (Input/Output, Three-State)
Defines the data portion of the bus transaction. DAS is
high during the address portion of a bus transaction
and low during the data portion. The LOW-to-HlGH
transition can be used by a Slave device to strobe bus
data into a register. DAS is driven only as a Bus Master.
HLDA
Bus Hold Acknowledge (Input)
A response to HOLD. When HLDA is LOW in response
to the chip’s assertion of HOLD, the chip is the Bus
Master.
During Bus Master operation, the C-LANCE waits for
HLDA to be deasserted HIGH before reasserting
HOLD LOW. This insures proper bus handshake under
all situations.
HOLD/BUSRQ
Bus Hold Request (Output, Open Drain)
Asserted by the C-LANCE when it requires access to
memory. HOLD is held LOW for the entire ensuing bus
transaction. The function of this pin is programmed
through bit (00) of CSR3. Bit (00) of CSR3 is cleared
when RESET is asserted.
When CSR3 (00) BCON = 0
PIN 17 = HOLD
(Output Open Drain and input sense) (48-Pin DIPs)
When CSR3 (00) BCON = 1
PIN 17 = BUSRQ (I/O Sense, Open Drain) (48-Pin DlPs)
If the C-LANCE wants to use the bus, it looks at HOLD/
BUSRQ; if it is HIGH the C-LANCE can pull it LOW and
request the bus. If it is already LOW, the C-LANCE
waits for it to go inactive-HlGH before requesting the
bus.
INTR
Interrupt (Output, Open Drain)
An attention signal that indicates, when active, that one
or more of the following CSR0 status flags is set: BABL,
MERR, MISS, RINT, TINT or IDON. INTR is enabled by
bit 06 of CSR0 (INEA = 1). INTR remains asserted until
the source of Interrupt is removed.
RCLK
Receive Clock (Input)
A 10 MHz square wave synchronized to the Receive
data and only active while receiving an Input Bit
Stream.