AM79C972BKCW Advanced Micro Devices, AM79C972BKCW Datasheet - Page 124

• Manufacturer Part Number: AM79C972BKCW
• Description: PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
• Manufacturer: Advanced Micro Devices

CSR27: Next Receive Descriptor Address Upper
Bit
31-16
15-0
CSR28: Current Receive Descriptor Address Lower
Bit
31-16
15-0
CSR29: Current Receive Descriptor Address Upper
Bit
31-16
15-0
124
Name
RES
NRDAU
Name
RES
CRDAL
Name
RES
CRDAU
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next receive descriptor address
pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
current receive descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current receive descriptor ad-
dress pointer.
Am79C972
CSR30: Base Address of Transmit Ring Lower
Bit
31-16 RES
15-0
CSR31: Base Address of Transmit Ring Upper
Bit
31-16 RES
15-0
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16 RES
15-0
CSR33: Next Transmit Descriptor Address Upper
Bit
31-16 RES
15-0
Name
BADXL
Name
BADXU
Name
NXDAL
Name
NXDAU
zeros and read as undefined.
base address of the Transmit
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next transmit descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next transmit descriptor address
pointer.
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Contains the lower 16 bits of the