HI-8583 Holt Integrated Circuits, HI-8583 Datasheet - Page 4

• Manufacturer Part Number: HI-8583
• Description: (HI-8582 / HI-8583) ARINC 429 SYSTEM ON A CHIP
• Manufacturer: Holt Integrated Circuits

FUNCTIONAL DESCRIPTION (cont.)
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-8582 data
bus during data read or write operations. The following table
describes this mapping:
CR15=0
CR15=1
CR15=0
CR15=1
ARINC
ARINC
ARINC
ARINC
DATA
DATA
BUS
BUS
BIT
BIT
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
16 15 14 13 12 11 10
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
STATE
ZERO
NULL
ONE
FIGURE 1. ARINC RECEIVER INPUT
9
DIFFERENTIAL VOLTAGE
+2.5 Volts to -2.5 Volts
+6.5 Volts to +13 Volts
31 30 32
-6.5 Volts to -13 Volts
BYTE 1
BYTE 2
9
1
8
2
7
3
6
HOLT INTEGRATED CIRCUITS
4
5
5
4
HI-8582, HI-8583
6
3
7
2
8
1
4
If
data stream totaling 32 bits is accepted even with gaps between
bits. The protocol still requires a word gap as defined in 4. above.
The HI-8582 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
If the
specifications and rejects outside the tolerances. The way the logic
operation achieves this is described below:
NFD
PULSE FALL TIME
PULSE RISE TIME
3. Each data bit must follow its predecessor by not less than 8
samples and no more than 12 samples. In this manner the bit
rate is checked. With exactly 1MHz input clock frequency, the
acceptable data bit rates are as follows:
4. The Word Gap timer samples the Null shift register every 10
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the mini-
mum pulse width is guaranteed.
input clocks (80 for low speed) after the last data bit of a valid
reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
PULSE WIDTH
NFD
DATA BIT RATE MAX
DATA BIT RATE MIN
BIT RATE
is held low, frequency discrimination is disabled and any
pin is high, the HI-8582 accepts signals that meet these
100K BPS ± 1% 12K -14.5K BPS
HIGH SPEED
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
HIGH SPEED
125K BPS
83K BPS
34.5 to 41.7 µsec
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
LOW SPEED
10.4K BPS
15.6K BPS