UPD23C32080AL NEC, UPD23C32080AL Datasheet - Page 13

• Manufacturer Part Number: UPD23C32080AL
• Description: (UPD23C32040AL / UPD23C32080AL) 32M-BIT MASK-PROGRAMMABLE ROM
• Manufacturer: NEC

Read Cycle Timing Chart 2 (Page Access Mode)
Notes 1. The address differs depending on the product as follows.
Page address
A–1
A–1
2. During WORD mode, A–1 is O15.
3. t
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
Upper address
A2 to A20
A3 to A20
high impedance state output.
[ µ µ µ µ PD23C32040AL ]
[ µ µ µ µ PD23C32080AL ]
DF
Note 2
Note 2
Page access time
Page access time
O0 to O7,
O8 to O15
is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
µ PD23C32040AL
µ PD23C32080AL
, A0, A1
, A0, A1, A2
Part Number
Note 1
t
t
/OE or OE (Input)
PAC
PAC
Note 1
Note 4
/CE
(Output)
(Input)
(Input)
(Input)
Upper address (A2 to A20)
Upper address (A3 to A20)
Before t
Before t
inputs condition
inputs condition
High-Z
Upper address
A2 to A20
A3 to A20
t
t
PAC
ACC
ACC
ACC
t
Data Sheet M15772EJ3V0DS
CE
t
OE
Note 5
– t
– t
PAC
PAC
Data Out
t
OH
t
PAC
/CE input condition
/CE input condition
Note 5
µ µ µ µ PD23C32040AL, 23C32080AL
Before t
Before t
Data Out
A–1, A0, A1
A–1, A0, A1, A2
Page address
t
OH
CE
CE
– t
– t
PAC
PAC
address (A–1, A0, A1, A2)
/OE or OE input condition
/OE or OE input condition
Before stabilizing of page
Before stabilizing of page
address (A–1, A0, A1)
Data Out
t
OH
t
DF
Note 3
High-Z
13