K9F1208D0B Samsung semiconductor, K9F1208D0B Datasheet
K9F1208D0B
Related parts for K9F1208D0B
K9F1208D0B Summary of contents
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... Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you ...
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K9F1208R0B K9F1208B0B K9F1208U0B 64M x 8 Bit NAND Flash Memory PRODUCT LIST Part Number Vcc Range K9F1208R0B-G,J 1.65 ~ 1.95V K9F1208B0B-Y,P 2.5 ~ 2.9V K9F1208B0B-G,J K9F1208U0B-Y,P 2.7 ~ 3.6V K9F1208U0B-G,J K9F1208U0B-V,F FEATURES • Voltage Supply - 1.8V device(K9F1208R0B) : 1.65~1.95V ...
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K9F1208R0B K9F1208B0B K9F1208U0B PIN CONFIGURATION (TSOP1) K9F1208U0B-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE ...
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Package Dimensions PIN CONFIGURATION (WSOP1) K9F1208U0B-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE 17 ...
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K9F1208R0B K9F1208B0B K9F1208U0B PIN CONFIGURATION (FBGA) K9F1208X0B-GCB0,JCB0/GIB0,JIB0 N.C N.C N N.C N.C N N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE ...
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Package Dimensions 63-Ball FBGA (measured in millimeters) Top View 8.50 ±0.10 #A1 0.10MAX FLASH MEMORY Bottom View 8.50 ±0.10 0. 7.20 0. 4.00 0. (Datum (Datum ...
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K9F1208R0B K9F1208B0B K9F1208U0B PIN DESCRIPTION Pin Name I/O ~ I/O DATA INPUTS/OUTPUTS 0 7 (K9F1208X0B) The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z ...
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K9F1208R0B K9F1208B0B K9F1208U0B Figure 1-1. K9F1208X0B FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High ...
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K9F1208R0B K9F1208B0B K9F1208U0B Product Introduction The K9F1208X0B is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell ...
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K9F1208R0B K9F1208B0B K9F1208U0B Memory Map The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or ...
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K9F1208R0B K9F1208B0B K9F1208U0B ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F1208X0B-XCB0 Temperature Under Bias K9F1208X0B-XIB0 K9F1208X0B-XCB0 Storage Temperature K9F1208X0B-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, ...
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K9F1208R0B K9F1208B0B K9F1208U0B DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions tRC=50ns (K9F1208R0B : 60ns), Sequential Read Operating CE=V IL Current I =0mA OUT Program Erase Stand-by Current(TTL CE=V ...
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K9F1208R0B K9F1208B0B K9F1208U0B VALID BLOCK Parameter Symbol Valid Block Number N NOTE : device 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with ...
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K9F1208R0B K9F1208B0B K9F1208U0B PROGRAM / ERASE CHARACTERISTICS Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time NOTE : 1.Typical program time is defined as the time within ...
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K9F1208R0B K9F1208B0B K9F1208U0B AC CHARACTERISTICS FOR OPERATION Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE ...
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K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is ...
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K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rete.The following possible ...
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K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I ...
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K9F1208R0B K9F1208B0B K9F1208U0B Pointer Operation of K9F1208X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ ...
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K9F1208R0B K9F1208B0B K9F1208U0B System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and ...
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K9F1208R0B K9F1208B0B K9F1208U0B Device K9F1208X0B Command Latch Cycle CLE t CLS ALS ALE I/O X Address Latch Cycle t CLS CLE ALS ALE t I/O X I/O I/Ox ...
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K9F1208R0B K9F1208B0B K9F1208U0B Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Serial access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ...
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K9F1208R0B K9F1208B0B K9F1208U0B Status Read Cycle CLE t CLS I/O X READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address I/O 00h or 01h ...
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K9F1208R0B K9F1208B0B K9F1208U0B Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE ...
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K9F1208R0B K9F1208B0B K9F1208U0B Sequential Row Read Operation CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE I/O ...
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K9F1208R0B K9F1208B0B K9F1208U0B BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command t t BERS ...
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K9F1208R0B K9F1208B0B K9F1208U0B ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ 27 Preliminary FLASH MEMORY ...
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K9F1208R0B K9F1208B0B K9F1208U0B Multi-Plane Block Erase Operation CLE ALE RE I/O 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For ...
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K9F1208R0B K9F1208B0B K9F1208U0B Read ID Operation CLE CE WE ALE RE I/O 90h X Read ID Command Address. 1cycle ID Defintition Table Access command = 90H Description 1 Byte Maker Code st Device Code 2 Byte nd ...
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K9F1208R0B K9F1208B0B K9F1208U0B Copy-Back Program Operation CLE ALE RE I/O 00h Column Page(Row) Address Address R/B On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be ...
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K9F1208R0B K9F1208B0B K9F1208U0B Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with four address cycles. Once the command is ...
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K9F1208R0B K9F1208B0B K9F1208U0B Figure 7. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I & NOTE: 1) After data access on 2nd half array by ...
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K9F1208R0B K9F1208B0B K9F1208U0B Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I & Figure 9. Sequential Row Read1 Operation R/B I/O X 00h Start ...
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K9F1208R0B K9F1208B0B K9F1208U0B Figure 10. Sequential Row Read2 Operation R/B I/O Start Add.(4Cycle) X 50h & Don’t Care) PAGE PROGRAM The device is programmed ...
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K9F1208R0B K9F1208B0B K9F1208U0B BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address block address loading initiates the ...
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K9F1208R0B K9F1208B0B K9F1208U0B Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. ...
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K9F1208R0B K9F1208B0B K9F1208U0B Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and ...
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K9F1208R0B K9F1208B0B K9F1208U0B Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables ...
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K9F1208R0B K9F1208B0B K9F1208U0B ≈ ≈ ≈ ≈ ≈ ≈ FLASH MEMORY 39 Preliminary ...
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K9F1208R0B K9F1208B0B K9F1208U0B READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to ...
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K9F1208R0B K9F1208B0B K9F1208U0B Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code, Reserved(A5h), ...
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K9F1208R0B K9F1208B0B K9F1208U0B RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The ...
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K9F1208R0B K9F1208B0B K9F1208U0B READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read . The R/B pin is normally high but transitions to low after program ...
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K9F1208R0B K9F1208B0B K9F1208U0B 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V CC Rp(min, 1.8V part Rp(min, 2.7V part Rp(min, 3.3V part) = where I is the sum of the ...
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K9F1208R0B K9F1208B0B K9F1208U0B Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP ...