IBM25PPC440GX IBM Microelectronics, IBM25PPC440GX Datasheet - Page 45

• Manufacturer Part Number: IBM25PPC440GX
• Description: PowerPC 440GX Embedded Processor
• Manufacturer: IBM Microelectronics

PowerPC 440GX Embedded Processor Data Sheet
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
2/12/04
EOT0:3/TC0:3
PerAddr00:31
PerWBE0:3
PerBLast
PerCS0:7
PerData00:31
PerOE
PerPar0:3
PerReady
PerR/W
PerWE
Signal Name
End Of Transfer/Terminal Count.
Peripheral address bus used by PPC440GX when not in
external master mode, otherwise used by external
master.
Note: PerAddr00 is the most significant bit (msb) on this
bus.
External peripheral data bus byte enables.
Used by either the peripheral controller, DMA controller,
or external master to indicates the last transfer of a
memory access.
External peripheral device select.
Peripheral data bus used by PPC440GX when not in
external master mode, otherwise used by external
master.
Note: PerData00 is the most significant bit (msb) on this
bus.
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GX is the bus master, it enables the selected
DDR SDRAMs to drive the bus.
External peripheral data bus byte parity.
Used by a peripheral slave to indicate it is ready to
transfer data.
Used by the PPC440GX when not in external master
mode, as output by either the peripheral controller or
DMA controller depending upon the type of transfer
involved. High indicates a read from memory, low
indicates a write to memory.
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
Write Enable. Low when any of the four PerWBE0:3
signals are low.
(Part 5 of 8)
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
3.3V tolerant
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Type
Page 45 of 74
Preliminary
Notes
1, 5
1, 2
1, 4
1, 2
1
2
1
2
1
2