AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 24

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Initial Access Delay Configuration
The frequency configuration informs the device of
the number of clocks that must elapse after ADV# is
SECTOR PROTECTION
The Am29BDD160 features several levels of sector
protection, which can disable both the program and
erase operations in certain sectors or sector groups
Sector and Sector Groups
The distinction between sectors and sector groups is
fundamental to sector protection. Sector are individ-
ual sectors that can be individually sector protected/
un-protected. These are the outermost 4 kword boot
sectors, that is, SA0 to SA7 and SA38 to SA45. See
tables 11 and 12.
Sector groups are a collection of three or four adja-
cent 32 kword sectors. For example, sector group
SG8 is comprised of sector SA8 to SA10. When any
sector in a sector group is protected/unprotected,
every sector in that group is protection/unprotected.
See Tables 11 and 12.
Persistent Sector Protection
A command sector protection method that replaces
the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that re-
quires a password before changes to certain sectors
or sector groups are permitted
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CR8 = IND/WAIT# Configuration (WC) 0 = IND/WAIT# Asserted During Delay—Default 1 = IND/WAIT# Asserted One
Data Cycle Before Delay
CR7 = Burst Sequence (BS) 0 = Reserved 1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC) 0 = Reserved 1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R) These bits are reserved for future use. Set these bits to “0.”
CR2–CR0 = Burst Length (BL2–BL0) 000 = Reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit
(8-byte) Burst Data Transfer - x16 and x32 Linear 010 = 128 bit (16-byte) Burst Data Transfer - x16 and x32 Linear 011 =
256 bit (32-byte) Burst Data Transfer - x16 Linear Only and x32 Linear 100 = 512 bit (64-byte) Burst Data Transfer - x16
Linear Only - Default 101 = Reserved, burst accesses disabled (asynchronous reads only) 110 = Reserved, burst accesses
disabled (asynchronous reads only) 111 = Reserved
CR15
CR7
RM
BS
1
1
Reserve
CR14
CR6
CC
0
1
Table 10. Configuration Register After Device Reset
Reserve
CR13
IAD3
CR5
0
0
Reserve
CR12
IAD2
CR4
Am29BDD160G
1
0
driven active before data is available. This value is
determined by the input frequency.
WP# Hardware Protection
A write protect pin that can prevent program or
erase to the two outermost 8 Kbytes sectors in the
75% bank
All parts default to operate in the Persistent Sector
Protection mode. The customer must then choose if
the Persistent or Password Protection method is
most desirable. There are two one-time programma-
ble non -volatile bits th at define which sector
protection method will be used. If the customer de-
cides to contin ue u sing th e Persistent Sector
Protection method, driven active before data will be
available. This value is determined by the input clock
frequency. They must set the Persistent Sector
Protection Mode Locking Bit. This will perma-
nently set the part to operate only using Persistent
Sector Protection. If the customer decides to use the
password method, they must set the Password
Mode Locking Bit. This will permanently set the
part to operate only using password sector protec-
tion.
It is important to remember that setting either the
Persistent Sector Protection Mode Locking Bit
or the Password Mode Locking Bit permanently
selects the protection mode. It is not possible to
switch between the two methods once a locking bit
has been set. It is important that one mode is
explicitly selected when the device is first pro-
Reserve
CR11
IAD1
CR3
1
0
CR10
IAD0
CR2
BL2
1
1
CR9
DOC
CR1
BL1
0
0
CR8
CR0
BL0
WC
0
0