AM29BDS320G SPANSION [SPANSION], AM29BDS320G Datasheet
AM29BDS320G
Related parts for AM29BDS320G
AM29BDS320G Summary of contents
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Data Sheet October 1, 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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... Am29BDS320G 32 Megabit ( 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 0.17 µm process technology Enhanced VersatileIO™ — Device generates data output voltages and tolerates data input voltages as determined by the voltage on ...
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... General Description The Am29BDS320G Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This device uses a single V ory array. The device supports Enhanced V and outputs. A 12.0-volt V sired. The device can also be programmed in standard EPROM programmers. ...
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... The device electrically erases all bits within a sector simultaneously via Fowler- Nordheim tunnelling. The data is programmed using hot electron injection. October 1, 2003 27243B1 WP# locks sectors 0 and 1 (bottom boot device) or sec- IL Am29BDS320G detector that automat ...
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... Figure 16. Reduced Wait-State Handshaking Burst Mode Read Starting at an Even Address .............................................. 52 Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address................................................ 53 Asynchronous Read ..............................................................................54 Figure 18. Asynchronous Mode Read with Latched Addresses . 54 Figure 19. Asynchronous Mode Read................................... 55 Figure 20. Reset Timings................................................... 56 Am29BDS320G 27243B1 October 1, 2003 ...
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... Figure 32. Example of Wait States Insertion (Standard Handshaking Device) ........................................................ 68 Figure 33. Back-to-Back Read/Write Cycle Timings ............... 69 Erase and Programming Performance . . . . . . . . 70 FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 70 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 71 VBD064—64-ball Fine-Pitch Ball Grid Array (FBGA Package ..................................................................................71 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 72 Am29BDS320G 5 ...
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... See the AC Characteristics section of this data sheet for full specifications Am29BDS320G V = 1.65 – 1. 2.7 – 3. 1.65 – 1. Reduced Wait-state IACC ) Reduced Wait-state IACC ) ACC Am29BDS320G 54 MHz 40 MHz D3, D4 C3, C4 D8, D9 C8, C9 87.5 95 106 120 13 13.5 20 27243B1 October 1, 2003 ...
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... State CLK Control A20–A0 October 1, 2003 27243B1 RDY Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Timer Burst Address Counter Am29BDS320G DQ15–DQ0 Input/Output Buffers Data Latch Logic Y-Decoder Y-Gating Cell Matrix X-Decoder 7 ...
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... A20–A0 A20– Bank A Address Bank A X-Decoder Bank B Address Bank B X-Decoder Status Control X-Decoder Bank C Bank C Address X-Decoder Bank D Address Bank D Am29BDS320G DQ15–DQ0 OE# DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 27243B1 October 1, 2003 ...
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... DQ5 DQ12 A18 A20 DQ2 DQ10 DQ0 DQ8 CE CLK WP# AVD Am29BDS320G DQ15 DQ13 DQ6 DQ4 DQ11 DQ3 G3 H3 DQ9 DQ1 OE ...
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... Should accelerates programming; automatically ID places device in unlock bypass mode sectors. Should A20–A0 DQ15–DQ0 CLK WP# ACC CE# OE# WE# RDY RESET# AVD# Am29BDS320G , disables IL for all other conditions. , locks all IL for all other conditions. 16 27243B1 October 1, 2003 ...
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... Note: For the Am29BDS320G, the last digit of the speed grade specifies the V Speed options ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt V in “3” and “4” (e.g., D3, D4) indicate a 3.0 Volt V ...
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... X H HIGH HIGH HIGH Z ) Control IO ) control allows the host system to set the voltage IO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving . WE# should remain Am29BDS320G CLK (See DQ15–0 RESET# Note) AVD I/O H ...
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... ACC ) is the delay from the stable ad each burst access, what mode of burst IACC after the active edge of the first CLK cycle. Sub- IACC after the active edge of each successive clock BACC Am29BDS320G 12. 13 ...
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... See “Autoselect Com- mand Sequence” for details Table 2.) Table 2. Burst Address Groups Group Address Ranges 8 words 0-7h, 8-Fh, 10-17h, ... 16 words 0-Fh, 10-1Fh, 20-2Fh, ... 32 words 00-1Fh, 20-3Fh, 40-5Fh, ... Am29BDS320G 27243B1 October 1, 2003 ...
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... Burst Mode Configuration Register Command Se- section for more information. The device will Figure 33, “Back-to-Back Read/Write Cycle shows how read and write cycles may be initiated for simul- on this input, the device automatically enters the afore- ID Am29BDS320G , and OE and IL and OE ...
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... Note that the ACC pin must ns. The automatic sleep mode is independent of the ACC Am29BDS320G for all other conditions. IH section for more ) for read CE represents the automatic ...
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... WP# pin, the device reverts to whether the two IH , the device does not accept any write cycles. This pro- LKO power-up and power-down. The command register and all CC is greater than V CC Am29BDS320G ). If RESET# is held CC4 (not during READY after RESET# returns to Figure 20, Table 14, “Command ...
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... Alternatively, contact a sales office or representative for copies of these documents LKO , CE and OE during power up, the device does IL IH and V power-up or power-down se required during the entire V IL Am29BDS320G or WE and 27243B1 October 1, 2003 ...
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... Typical timeout per individual block erase 2 Typical timeout for full chip erase 2 Max. timeout for byte/word write 2 Max. timeout for buffer write 2 times typical N Max. timeout per individual block erase 2 Max. timeout for full chip erase 2 N Am29BDS320G Description Description µs N µ s (00h = not supported ...
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... Max. number of bytes in multi-byte write = 2 (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Am29BDS320G N 27243B1 October 1, 2003 ...
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... Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Bank Organization Number of banks Bank A Region Information Number of sectors in bank Bank B Region Information Number of sectors in bank Bank C Region Information Number of sectors in bank Bank D Region Information Number of sectors in bank Am29BDS320G 21 ...
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... Kwords 8 Kwords 8 Kwords 8 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS320G (x16) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh ...
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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Am29BDS320G (x16) Address Range 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh ...
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... Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 8K words 8K words 8K words 8K words Am29BDS320G (x16) Address Range 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1FDFFFh ...
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... October 1, 2003 27243B1 Table 14, “Command Definitions,” on page 36 “Erase Suspend/Erase Resume section for more information. 18 show the timings. Am29BDS320G “Reset Command” section and “Re- sections for more 25 ...
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... Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Set Burst Mode Configuration Register Command for Command for Synchronous Mode Asynchronous Mode (A19 = 0) (A19 = 1) Synchronous Read Mode Only Table 8). Am29BDS320G 27243B1 October 1, 2003 ...
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... Even Initial Odd Initial Odd Addr. Addr. Initial with with Addr. Boundary Boundary Am29BDS320G Device Speed Rating MHz MHz 8 27 ...
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... The device can be set so that the falling clock Typical No. of Clock Cycles after Table 11. Burst Read Mode Settings A16 Am29BDS320G AVD# Low 40/54 MHz Address Bits A15 0 ...
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... Data is valid on the 5th active CLK edge after AVD# transition to V 100 = Data is valid on the 6th active CLK edge after AVD# transition to V 101 = Data is valid on the 7th active CLK edge after AVD# transition unlock ( Am29BDS320G whenever there ...
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... BA represents the bank address, and SA represents the sector ad- dress. The device ID is read in three cycles shows the address and data re- Am29BDS320G 27243B1 October 1, 2003 ...
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... Address (BA) + 00h (BA) + 01h 2222h (1 2223h (1 (BA) + 0Eh 2214h (3 2234h (3 (BA) + 0Fh (SA) + 02h 43h (reduced wait-state), (BA) + 03h Table 14 section for information on these sta- Am29BDS320G Read Data 0001h 227Eh , top boot bottom boot top boot bottom boot) IO 2200h 0001 (locked), 0000 (unlocked) ...
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... Table 14, “Command Definitions,” this input, the device automatically enters the Unlock ID START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Figure 2. Erase Operation Am29BDS320G for timing 27243B1 October 1, 2003 ...
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... The system can determine the status of the erase operation by reading October 1, 2003 27243B1 Table 14, “Command Definitions,” on page 36 Table 14 for details on the unlock bypass com- Table 14 42.). The time-out begins from Am29BDS320G shows the address 33 ...
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... Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing “Write Operation Status” sec- “Write Operation Status” section for more information. sections for details. Am29BDS320G 27243B1 October 1, 2003 ...
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... Note: See Table 14 October 1, 2003 27243B1 START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed for program command sequence. Figure 3. Program Operation Am29BDS320G No Yes Yes 35 ...
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... Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. , and 2214 for 3 Am29BDS320G Fourth Fifth Addr Data Addr Data Addr ...
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... Embedded Algorithm),” on page 64 shows the Data# Polling timing diagram. October 1, 2003 27243B1 Table 16, “Write Operation Status,” “ the AC Characteristics section Am29BDS320G ...
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... START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No PASS FAIL Figure 4. Data# Polling Algorithm Am29BDS320G 27243B1 October 1, 2003 ...
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... Embedded Algorithm),” on page 64 Table 15, “DQ6 and DQ2 Indications,” on page October 1, 2003 27243B1 (toggle bit timing diagram), and 41. Am29BDS320G “ ...
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... START Read DQ7–DQ0 Read DQ7–DQ0 No Toggle Bit = Toggle? Yes DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit No = Toggle? Yes Program/Erase Operation Not Program/Erase Complete, Write Operation Complete Reset Command Figure 5. Toggle Bit Algorithm Am29BDS320G 27243B1 October 1, 2003 ...
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... Table 15. DQ6 and DQ2 Indications then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, Am29BDS320G and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. ...
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... The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in non-erase-suspended mode Table 16. Write Operation Status DQ7 (Note 2) DQ6 DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am29BDS320G DQ5 DQ2 (Note 1) DQ3 (Note 2) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data ...
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... V for periods during voltage SS +0.5 V for periods ns. See CC + 2.0 V for periods ns. See +2 +0.5 V 2.0 V Figure 7. Maximum Positive Overshoot Waveform ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85° +2.7 to +3.15 V Am29BDS320G + 0 0.5 V. During voltage ...
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... CC min min I = –100 µ min min = V max CC ns. Typical sleep mode current is equal to I ACC Am29BDS320G Min Typ. Max max ±1 max ± 0 MHz MHz 3 ...
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... Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Input Measurement Level IO Am29BDS320G Table 17. Test Specifications All Speed Options Unit 0.0– ...
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... Setup Time VIOS IO t RESET# Low Hold Time RSTH RESET# Figure 10 Test Setup Min Min Min t VCS t VIOS t RSTH and V Power-up Diagram CC IO Am29BDS320G Speed Unit 50 µs 50 µs 50 µs 27243B1 October 1, 2003 ...
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... MHz) Max D8, D9 (54 MHz) Max Max Min Min Min Max Max 10 Max 10 Min Min 5 Max 13.5 Min Min Min Min Min Max Am29BDS320G (54 MHz) (40 MHz) (40 MHz) Unit 87.5 95 D3, D4 C8, C9 C3, C4 (54 MHz) (40 MHz) (40 MHz) Unit 106 120 13 13 ...
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... The device is in synchronous mode. Figure 11. CLK Synchronous Burst Mode Read cycles for initial access shown IACC t ACC t OE (rising active CLK) Am29BDS320G t CEZ 7 t BDH t BACC OEZ t RACC t RDYS ...
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... In the Burst Mode Configuration Register, A17 = 0. Figure 12. CLK Synchronous Burst Mode Read October 1, 2003 27243B1 cycles for initial access shown AVD IACC t ACC t t RACC OE t RDYS (Falling Active Clock) Am29BDS320G t CEZ BDH t BACC Hi OEZ Hi-Z 49 ...
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... IACC t ACC Figure 13. Synchronous Burst Mode Read 7 cycles for initial access shown. 18.5 ns typ. (54 MHz IACC t ACC t RACC t RDYS Am29BDS320G t CEZ BDH t BACC OEZ t RACC t RDYS t BDH t BACC ...
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... Figure 15. Burst with RDY Set One Cycle Before Data October 1, 2003 27243B1 wait cycles for initial access shown typ. (40 MHz IACC t ACC t RACC RDYS Am29BDS320G t CEZ t BDH t BACC OEZ Hi-Z Hi-Z 51 ...
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... CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst Mode Read cycles for initial access shown IACC t ACC t OE Starting at an Even Address Am29BDS320G t CEZ BDH t BACC OEZ t RACC ...
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... This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode. October 1, 2003 27243B1 cycles for initial access shown IACC t ACC t OE Starting at an Odd Address Am29BDS320G t CEZ BDH t BACC OEZ t RACC t ...
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... Min Min Min Max Read Min Toggle and Min Data# Polling Max Min OEH t CE Valid RD t ACC CAS AAVDH t AVDP t AAVDS Am29BDS320G D3, D4 C3, C4 D8, D9 C8, C9 (54 MHz) (40 MHz) Unit 13 10.5 ...
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... AC Characteristics CE# OE# WE# DQ15-DQ0 A20-A0 AVD# Note Read Address Read Data. October 1, 2003 27243B1 OEH ACC RA Figure 19. Asynchronous Mode Read Am29BDS320G t OEZ Valid RD 55 ...
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... CE#, OE# RESET Description Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 20. Reset Timings Am29BDS320G All Speed Options Unit Max 35 µs Max 500 ns Min 500 ns Min 200 ns Min 20 µ ...
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... AVD# or the active edge of CLK. 3. See the “Erase and Programming Performance” section for more information. 4. Does not include the preprogramming time. October 1, 2003 27243B1 Synchronous Asynchronous Synchronous Asynchronous Am29BDS320G All Speed Options Unit Min ...
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... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 21. Asynchronous Program Operation Timings AVHW t AVDP PA A0h WPH t WC Am29BDS320G Read Status Data Complete Progress t WHWH1 27243B1 October 1, 2003 ...
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... The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. Figure 22. Alternate Asynchronous Program Operation Timings October 1, 2003 27243B1 AVDP WPH t WC Am29BDS320G Read Status Data Complete Progress t WHWH1 59 ...
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... CLK must not have an active edge while WE AVD# must toggle during command sequence unlock cycles. Figure 23. Synchronous Program Operation Timings WPH Am29BDS320G Read Status Data Complete Progress t WHWH1 27243B1 October 1, 2003 ...
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... AH 9. CLK must not have an active edge while WE Figure 24. Alternate Synchronous Program Operation Timings October 1, 2003 27243B1 (Note 8) AVDP PA A0h WPH Am29BDS320G Read Status Data Complete Progress t WHWH1 61 ...
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... Address bits A20 –A12 are don’t cares during unlock cycles in the command sequence 555h for 10h for chip erase chip erase 30h WPH t WC Am29BDS320G Read Status Data Complete Progress t WHWH2 27243B1 October 1, 2003 ...
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... Don't Care OE ACC Note: Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing October 1, 2003 27243B1 A0h Don't Care t VIDS t VID Am29BDS320G PA PD Don't Care 63 ...
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... AVD# must toggle between data reads. Figure 28. Toggle Bit Timings (During Embedded Algorithm CEZ t OEZ Status Data CE Status Data Am29BDS320G VA Status Data VA Status Data 27243B1 October 1, 2003 t CEZ t OEZ ...
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... RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RDY is active one clock cycle before data. 4. AVD# must toggle between data reads. Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings October 1, 2003 27243B1 IACC Status Data Am29BDS320G t IACC Status Data 65 ...
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... Figure 30. Latency with Boundary Crossing C62 C63 C63 C63 RACC latency t t RACC RACC latency D61 D62 D63 Am29BDS320G C64 C65 C66 RACC D64 D65 D66 27243B1 October 1, 2003 C67 43 D67 ...
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... Figure 31. Latency with Boundary Crossing October 1, 2003 27243B1 C62 C63 C63 C63 RACC latency t t RACC RACC latency D61 D62 D63 into Program/Erase Bank Am29BDS320G C64 RACC Invalid Read Status 67 ...
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... total number of clock cycles following AVD# falling edge number of clock cycles programmed Am29BDS320G D0 D1 Rising edge of next clock cycle following last wait state triggers next burst data 27243B1 October 1, 2003 ...
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... October 1, 2003 27243B1 Read status (at least two cycles) in same bank and/or array data from other bank OEH t OEZ t ACC t t OEH SR/W RA Am29BDS320G Begin another write or program command sequence GHWL RD RA 555h AAh 69 ...
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... C, 1 1.65 V, 1,000,000 cycles. CC Test Setup OUT V IN Test Conditions 150°C 125°C Am29BDS320G Unit Comments s Excludes 00h programming prior to erasure (Note 4) s Excludes system level µs overhead (Note 5) µs Excludes system level s overhead (Note million cycles. Additionally, ...
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... RESPECTIVELY 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am29BDS320G ...
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... FASL. The information in this document is subject to change without notice. Product and Company names are trademarks or registered trademarks of their respective owners Copyright 2003 FASL LLC. All rights reserved Am29BDS320G 27243B1 October 1, 2003 ...