AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 18

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

16
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Input
cycle program command sequence as required by the Unlock Bypass mode. Re-
moving V
sectors must be unlocked prior to raising ACC to V
not be at V
age may result. In addition, the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
When at V
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Autoselect
mode may only be entered and used when in the asynchronous read mode. Refer
to the
information.
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are
both held at V
access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. While in synchronous mode, the de-
vice automatically enables this mode when either the first active CLK edge occurs
after t
required to provide new data.
I
sleep mode current specification.
The RESET# input provides a hardware method of resetting the device to reading
array data. When RESET# is driven low for at least a period of t
mediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
CC3
CC4
in the DC Characteristics table represents the standby current specification.
in the
ACC
“Autoselect Command Sequence” section on page 31
ID
or the CLK runs slower than 5MHz. Note that a new burst operation is
IL
ID
from the ACC input returns the device to normal operation. Note that
, ACC locks all sectors. ACC should be at V
“DC Characteristics” section on page 45
for operations other than accelerated programming, or device dam-
CC
± 0.2 V. The device requires standard access time (t
ACC
+ 60 ns. The automatic sleep mode is independent of the
Am29BDS640G
P r e l i m i n a r y
ID
. Note that the ACC pin must
represents the automatic
IH
for all other conditions.
RP
section for more
, the device im-
CE
) for read
25903C1 October 1, 2003