AM29BDS640G SPANSION [SPANSION], AM29BDS640G Datasheet - Page 75

• Manufacturer Part Number: AM29BDS640G
• Description: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

Revision Summary
October 1, 2003 25903C1
Revision A (February 13, 2002)
Revision A+1 (February 19, 2002)
Revision A+2 (February 27, 2002)
Revision A+3 (May 9, 2002)
Initial release.
Automatic Sleep Mode
Clarified description to indicate that sleep mode is activated when the first CLK
edge occurs after t
Figure 20, Asynchronous Program Operation Timings
Modified to show that CLK is don’t care prior to AVD# going low, and that AVD#
must not be low before CE# transitions low.
Figure
Extended don’t care section of CLK to falling edge of WE#.
Requirements for Synchronous (Burst) Read Operation
Shifted address, clock, and data cycle references in third paragraph up by one.
Table 4, System Interface String
Corrected data for address 23h.
Table 9, Initial Access Cycles vs. Frequency
Added table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Table 13, Command Definitions
Added bottom boot device IDs to table.
RDY: Ready
Corrected address boundary from 63rd word/3Eh to 64th word/3Fh.
DC Characteristics
Added V
Erase/Program Operations table
Added specifications for parameters t
Figures 21, 23
Added note to indicate AVD# must toggle during command sequence unlock cy-
cles. Added t
Figures 22, 24
Added figures, which show different timings between addresses, CLK, WE#, and
AVD#.
Figures 25, 27, 28
Added note to indicate AVD# must toggle during data reads.
Figures 30, 31
Shifted address, clock, and data cycle counts up by one.
21, Asynchronous Program Operation Timings
IO
= V
CSW1
IO min
to 21.
ACC
P r e l i m i n a r y
to test conditions for V
.
Am29BDS640G
CSW1
, t
OL
CSW2
and V
, t
CHW
OH
, t
in table.
AHC
.
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