GS8161Z18 GSI [GSI Technology], GS8161Z18 Datasheet

GS8161Z18

Manufacturer Part Number

GS8161Z18

Description

18Mb Pipelined and Flow Through Synchronous NBT SRAM

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8161Z18.pdf (36 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin-compatible with both pipelined and flow through

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA

Functional Description

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is an

18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like

ZBT, NtRAM, NoBL or other pipelined read/double late write

or flow through read/single late write SRAMs, allow

utilization of all available bus bandwidth by eliminating the

need to insert deselect cycles when the device is switched from

read to write cycles.

Rev: 2.15 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization

NtRAM™, NoBL™ and ZBT™ SRAMs

packages

Through

Pipeline

3-1-1-1

2-1-1-1

18Mb Pipelined and Flow Through

3.3 V

2.5 V

Flow

3.3 V

2.5 V

Synchronous NBT SRAM

Curr

tCycle

(x32/x36)

(x18)

Parameter Synopsis

1/36

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

5.5

255

300

250

295

165

190

165

190

2.7

4.4

6.0

GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) may

be configured by the user to operate in Pipeline or Flow

Through mode. Operating as a pipelined synchronous device,

in addition to the rising-edge-triggered registers that capture

input signals, the device incorporates a rising-edge-triggered

output register. For read cycles, pipelined SRAM output data is

temporarily stored by the edge triggered output register during

the access cycle and then released to the output drivers at the

next rising edge of clock.

The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is

implemented with GSI's high performance CMOS technology

and is available in JEDEC-standard 100-pin TQFP and

165-bump FP-BGA packages.

230

270

230

265

160

180

160

180

3.0

5.0

6.5

200

230

195

225

150

170

150

170

3.4

6.0

7.0

185

215

180

210

145

165

145

165

3.8

6.7

7.5

165

190

165

185

135

150

135

150

4.0

7.5

8.5

250 MHz–133 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

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