GS8161Z18 GSI [GSI Technology], GS8161Z18 Datasheet - Page 25

• Manufacturer Part Number: GS8161Z18
• Description: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: GSI [GSI Technology]

Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Rev: 2.15 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Bit #
x36
x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
Revision
X
X
Code
Die
X
X
X
X
TDI
TMS
TCK
0
0
0
0
·
·
0
0
·
X
X
1
1
·
Not Used
0
0
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
2
31 30 29
0
JTAG TAP Block Diagram
Boundary Scan Register
·
0
0
1
0
Control Signals
1
1
25/36
·
·
0
0
· · ·
0
0
·
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
2
0
0
1
0
0
0
·
1
1
Configuration
·
0
0
I/O
0
1
·
0
0
0
0
·
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
GSI Technology
TDO
JEDEC Vendor
ID Code
© 1998, GSI Technology
0
1
1