LF2249 LODEV [LOGIC Devices Incorporated], LF2249 Datasheet - Page 3

• Manufacturer Part Number: LF2249
• Description: 12 x 12-bit Digital Mixer
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
Outputs
S
The current 16-bit result is available
on the S
may be either the upper or lower 16
bits of the accumulator output, de-
pending on the state of SWAP. The
LSB is S
Controls
ENA–END — Pipeline Register Enable
Input data in the
input register is latched into the corre-
sponding pipeline register stack on
each rising edge of CLK for which EN
is LOW. Data already in the
stack is pushed down one register posi-
tion. When EN
the
change, and the data in the
register will not be stored in the register
stack.
ADEL
N
registered pipeline delay select word.
N
pipeline register stack is routed to the
multiplier inputs. The minimum delay
is one clock cycle (
the maximum delay is 16 clock cycle
(
values of ADEL–DDEL and the con-
tents of the pipeline register stacks are
unknown and must be initialized by the
user.
N
15-0
DEL (
DEL determines which stage of the
DEL = 1111). Upon power up, the
N
— Data Output
pipeline register stack does not
3-0
N
15-0
0
–DDEL
= A, B, C, or D) is the 4-bit
(Figure 1b).
outputs. The output data
N
3-0
N
is HIGH, the data in
— Pipeline Delay
N
(
N
DEL = 0000), and
Select
= A, B, C, or D)
N
N
register
input
N
N
NEG
The NEG
mine whether a subtraction or accumu-
lation of products is performed. When
NEG
negated, causing the product to be sub-
tracted from the accumulator contents.
Likewise, when NEG
product C x D is negated, causing the
product to be subtracted as well. NEG
and NEG
be performed on the data input during
the current clock cycle when ADEL–
DDEL = 0000.
CASEN — Cascade Enable
When CASEN is LOW, data being in-
put on the CAS
clock cycle will be registered and accu-
mulated internally. When CASEN is
HIGH, the CAS
FT — Feedthrough Control
When FT is LOW and ADEL–DDEL =
0000, data being input on the CAS
inputs is delayed three clock cycles to
align the data with the data being input
on the A
HIGH, the cascade data being input is
routed around the three delay registers
to simplify the cascading of multiple
devices.
1
1
–NEG
is HIGH, the product A x B is
11-0
2
1
determine the operation to
2
and NEG
–D
— Negate Control
11-0
15-0
15-0
inputs. When FT is
3
inputs are ignored.
inputs during that
2
2
controls deter-
is HIGH, the
15-0
1
ACC — Accumulator Control
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output.
HIGH, the emerging products are
added to the sum of the previous prod-
ucts.
RND — Rounding Control
When RND is HIGH, the sum of the
products of the data being input on
the current clock cycle will be
rounded to 16 bits. To avoid the accu-
mulation of roundoff errors, round-
ing is only performed during the first
cycle of each accumulation process.
SWAP — Output Select
The SWAP control allows the user to
access all 24 bits of the accumulator
output by switching between upper
and lower 16-bit words. When SWAP
is HIGH, the upper 16 bits of the accu-
mulator are always output. When
SWAP is LOW, the lower 16 bits of the
accumulator are output on every
other clock cycle. As long as SWAP
remains LOW, new output data will
not be clocked into the output regis-
ters.
OE — Output Enable
When the OE signal is LOW, the
current data in the output registers
is available on the S
OE is HIGH, the outputs are in a
high-impedance state.
Video Imaging Products
12 x 12-bit Digital Mixer
15-0
When ACC is
08/16/2000–LDS.2249-J
pins. When
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