CY62167EV30LL45BVXI Cypress Semiconductor Corporation., CY62167EV30LL45BVXI Datasheet

CY62167EV30LL45BVXI

Manufacturer Part Number

CY62167EV30LL45BVXI

Description

BGA48

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY62167EV30LL45BVXI.pdf (13 pages)

Specifications of CY62167EV30LL45BVXI

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Features

■

Functional Description

The CY62167EV30 is a high performance CMOS static RAM

organized as 1M words by 16 bits/2M words by 8 bits. This

device features an advanced circuit design designed to provide

an ultra low active current. Ultra low active current is ideal for

providing More Battery Life™ (MoBL

Logic Block Diagram

Cypress Semiconductor Corporation

Document #: 38-05446 Rev. *D

TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM

Very high speed: 45 ns

Wide voltage range: 2.20V–3.60V

Ultra low standby power

❐

Ultra low active power

❐

Easy memory expansion with CE

Automatic power down when deselected

CMOS for optimum speed/power

Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I packages

Typical standby current: 1.5 µA

Maximum standby current: 12 µA

Typical active current: 2.2 mA @ f = 1 MHz

Power Down

Circuit

, CE

) in portable applications

, and OE features

•

BHE

BLE

198 Champion Court

COLUMN DECODER

DATA IN DRIVERS

1M × 16 / 2M x 8

RAM Array

16-Mbit (1M x 16 / 2M x 8) Static RAM

such as cellular telephones. The device also has an automatic

power down feature that reduces power consumption by 99%

when addresses are not toggling. Place the device into standby

mode when deselected (CE

BLE are HIGH). The input and output pins (IO

placed in a high impedance state when: the device is deselected

(CE

Byte High Enable and Byte Low Enable are disabled (BHE, BLE

HIGH), or a write operation is in progress (CE

and WE LOW).

To write to the device, take Chip Enables (CE

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from IO pins (IO

into the location specified on the address pins (A

If Byte High Enable (BHE) is LOW, then data from the IO pins

(IO

address pins (A

To read from the device, take Chip Enables (CE

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on IO

memory appears on IO

for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress

application note

through IO

HIGH or CE

•

to IO

San Jose

. If Byte High Enable (BHE) is LOW, then data from

AN1064, SRAM System

through A

) is written into the location specified on the

LOW), outputs are disabled (OE HIGH), both

CA 95134-1709

to IO

CY62167EV30 MoBL

HIGH or CE

. See the

Revised September 14, 2007

BLE

BYTE

BHE

–IO

“Truth Table” on page 9

Guidelines.

LOW or both BHE and

through IO

•

through IO

LOW, CE

LOW and CE

408-943-2600

through A

) is written

HIGH

) are

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