74VCXH16373TTR STMicroelectronics, 74VCXH16373TTR Datasheet

IC LATCH 16BIT LV D 48-TSSOP

74VCXH16373TTR

Manufacturer Part Number
74VCXH16373TTR
Description
IC LATCH 16BIT LV D 48-TSSOP
Manufacturer
STMicroelectronics
Series
74VCXHr
Datasheet

Specifications of 74VCXH16373TTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.3 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1ns
Current - Output High, Low
18mA, 18mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1100-2
DESCRIPTION
The 74VCXH16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate
technology. It is ideal for low power and very high
speed 2.3 to 3.6V applications; it can be interfaced
to 3.6V signal environment for both inputs and
outputs.
These 16 bit D-TYPE latches are bite controlled
by two latch enable inputs (nLE) and two output
enable inputs (OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Bus hold on data inputs is provided in order to
eliminate the need for external pull-up or
pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
|I
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H16373
BUS HOLD PROVIDED ON DATA INPUTS
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PD
OH
OH
CC
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
= 3.0 ns (MAX.) at V
= 3.4 ns (MAX.) at V
| = I
| = I
and
(OPR) = 2.3V to 3.6V
OL
OL
five-layer
= 24mA (MIN) at V
= 18mA (MIN) at V
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
metal
CC
CC
= 3.0 to 3.6V
= 2.3 to 2.7V
CC
CC
wiring
= 3.0V
= 2.3V
C
2
MOS
ORDER CODES
PIN CONNECTION
PACKAGE
TSSOP
74VCXH16373
TUBE
TSSOP
74VCXH16373TTR
T & R
1/12

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74VCXH16373TTR Summary of contents

Page 1

... All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 = 3.0 to 3.6V = 2.3 to 2. 2.3V CC ORDER CODES PACKAGE TSSOP PIN CONNECTION 2 wiring C MOS 74VCXH16373 TSSOP TUBE T & R 74VCXH16373TTR 1/12 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, ...

Page 3

LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage (OFF State Output Voltage (High or ...

Page 4

DC SPECIFICATIONS (2.7V < V Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Input Hold ...

Page 5

DC SPECIFICATIONS (2.3V < V Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Input Hold Current ...

Page 6

AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter t t Propagation Delay PLH PHL Time Propagation Delay PLH PHL Time Output Enable Time PZL PZH t t Output Disable Time PLZ ...

Page 7

TEST CIRCUIT PLH PHL 3.0 to 3.6V) PZL PLZ 2.3 to 2.7V) PZL PLZ PZH PHZ equivalent ...

Page 8

WAVEFORM PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 8/12 ...

Page 9

WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 74VCXH16373 9/12 ...

Page 10

DIM. MIN 0. 0.17 c 0. 0˚ PIN 1 IDENTIFICATION 1 10/12 TSSOP48 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 0.9 0.27 ...

Page 11

Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. TYP A C 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 inch MAX. MIN. TYP. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 ...

Page 12

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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