74HC595D,118 NXP Semiconductors, 74HC595D,118 Datasheet - Page 18
![IC SHIFT REGISTER 8BIT 16SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
74HC595D,118
Manufacturer Part Number
74HC595D,118
Description
IC SHIFT REGISTER 8BIT 16SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet
1.74HC595D118.pdf
(28 pages)
Specifications of 74HC595D,118
Package / Case
16-SOIC (3.9mm Width)
Logic Type
Shift Register
Output Type
Standard
Function
Serial to Parallel
Number Of Elements
1
Number Of Bits Per Element
8
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Counting Sequence
Serial to Serial/Parallel
Number Of Circuits
1
Logic Family
HC
Propagation Delay Time
16 ns
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1483-2
74HC595D-T
935009160118
74HC595D-T
935009160118
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74HC595D,118
Manufacturer:
NXP Semiconductors
Quantity:
2 000
Part Number:
74HC595D,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
2003 Jun 25
t
t
t
t
f
T
t
t
t
t
t
t
t
t
f
W
su
h
rem
max
PHL
PHL
PZH
PHZ
W
su
h
rem
max
amb
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
SYMBOL
/t
/t
/t
PLH
PZL
PLZ
= 40 to +125 C
shift clock pulse width
HIGH or LOW
storage clock pulse width
HIGH or LOW
master reset pulse width
LOW
set-up time DS to SH_CP
set-up time
SH_CP to ST_CP
hold time DS to SH_CP
removal time
MR to SH_CP
maximum clock
pulse frequency
SH_CP or ST_CP
propagation delay
SH_CP to Q7’
propagation delay
ST_CP to Qn
propagation delay
MR to Q7’
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
shift clock pulse width
HIGH or LOW
storage clock pulse width
HIGH or LOW
master reset pulse width
LOW
set-up time DS to SH_CP
set-up time
SH_CP to ST_CP
hold time DS to SH_CP
removal time
MR to SH_CP
maximum clock
pulse frequency
SH_CP or ST_CP
PARAMETER
see Fig.7
see Fig.8
see Fig.10
see Fig.9
see Fig.8
see Fig.9
see Fig.10
see Figs 7 and 8
see Fig.7
see Fig.8
see Fig.10
see Fig.11
see Fig.11
see Fig.7
see Fig.8
see Fig.10
see Fig.9
see Fig.8
see Fig.9
see Fig.10
see Figs 7 and 8
WAVEFORMS
TEST CONDITIONS
18
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
V
CC
(V)
20
20
25
20
20
3
13
24
24
24
30
24
24
3
15
20
MIN.
74HC595; 74HCT595
TYP.
Product specification
63
60
60
53
45
MAX.
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
UNIT